MD5811-D256-V3Q18-X SanDisk, MD5811-D256-V3Q18-X Datasheet - Page 33

• Manufacturer Part Number: MD5811-D256-V3Q18-X
• Description: IC MDOC P3 256MB 48-TSOP
• Manufacturer: SanDisk

Specifications of MD5811-D256-V3Q18-X

• Format - Memory: FLASH
• Memory Type: FLASH - Nand
• Memory Size: 256M (32M x 8)
• Speed: 55ns
• Interface: Parallel
• Voltage - Supply: 2.5 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-TSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

The LATENCY bit is the third bit that must be set in the MultiBurst Mode Control register. When
the LATENCY bit is set to 0, the host can latch the first 16-bit data word two clock cycles after
CLK0. This time can be extended by up to seven clock cycles by programming the LATENCY bit.
After latching the first word, additional 16-bit data words can be latched on each subsequent clock
cycle.
The HOLD bit in the MultiBurst Mode Control register can be set to hold each data word valid for
two clock cycles rather than one.
The LENGTH bit in the MultiBurst Mode Control register must be programmed with the length of
the burst to be performed. As read cycles from the flash are volatile, each burst cycle must read
exactly this number of words.
The CLK input can be toggled continuously or can be halted. When halting the CLK input, the
following guidelines must be observed:
•
•
•
•
4.2
Mobile DiskOnChip P3 provides a DMARQ# output that enables up to 32KB to be read from the
flash by the host DMA controller. During DMA operation, the DMARQ# output is used to notify
the host DMA controller that the next flash page is ready to be read, and the IRQ# pin indicates
whether an error occurred while reading the data from the flash or the end of the DMA transfer was
reached.
The DMARQ# output sensitivity is chosen by setting the EDGE bit in the DMA Control register[0]:
•
•
The following steps are required to initiate a DMA operation:
1.
30
After asserting OE# and CE#, LATENCY + 2 CLK cycles are required prior to latching the
first word (2.5 CLK cycles if CLK_INV is set to 1).
If the HOLD bit is set to 0, the host must provide one rising CLK edge for each word read,
except for the last word latched, for which CLK does not need to be toggled.
If the HOLD bit is set to 1, the host must provide two rising CLK edges for each word read,
except for the last word, for which the second of the two CLK rising edges is not required.
Subsequent toggling of the CLK is optional.
Edge − The DMARQ# output pulses to logic 0 for 250~500 nsec to indicate to the DMA
controller that a flash page is ready to be read. The EDGE bit is set to 1 for this mode.
Level − The DMARQ# output is asserted to initiate the block transfer and returns to the
negated state at the end of each block transfer. The EDGE bit is set to 0 for this mode.
Initialize the platform’s DMA controller to transfer 512 bytes upon each assertion of the
DMARQ# output. If the DMA controller supports an edge-sensitive DMARQ# signal, then
initialize the DMA controller to transfer 512 bytes upon each DMA request. If the DMA
controller supports a level-sensitive DMARQ# signal, then initialize the DMA controller to
transfer data while DMARQ# is asserted.
DMA Operation
Data Sheet, Rev. 0.3
Mobile DiskOnChip P3
93-SR-009-8L