MD5811-D256-V3Q18-X SanDisk, MD5811-D256-V3Q18-X Datasheet - Page 57

• Manufacturer Part Number: MD5811-D256-V3Q18-X
• Description: IC MDOC P3 256MB 48-TSOP
• Manufacturer: SanDisk

Specifications of MD5811-D256-V3Q18-X

• Format - Memory: FLASH
• Memory Type: FLASH - Nand
• Memory Size: 256M (32M x 8)
• Speed: 55ns
• Interface: Parallel
• Voltage - Supply: 2.5 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-TSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

8.16 MultiBurst Mode Control Register
Description:
Address (hex): 101C
54
Read/Write
Description
Reset Value
Read/Write
Description
Reset Value
Bit No.
12-15
8-11
3-7
0
1
2
BST_EN (MultiBurst Mode Enable). Enables MultiBurst mode read cycles.
0: The CLK input is disabled and may be left floating. Burst read cycles are not supported.
1: The CLK input is enabled. Subsequent read cycles must be MultiBurst mode.
CLK_INV (Clock Invert). Selects the edge of the CLK input on which CE# and OE# are
sampled.
0: CE# and OE# are sampled on the rising edge of CLK.
1: CE# and OE# are sampled on the falling edge of CLK, and there will be an additional ½
HOLD. Specifies if the data output on D[15:0] during MultiBurst mode read cycles should be
held for an additional clock cycle.
0: Data on the D[15:0] outputs is held for one clock cycle
1: Data on the D[15:0] outputs is held for two clock cycles
Reserved for future use.
LATENCY. Controls the number of clock cycles between when Mobile DiskOnChip P3
samples OE# and CE# asserted and the first word of data is available to be latched by the
host. This number of clock cycles is equal to 2 + LATECNCY. If HOLD = 1, then the data is
available to be latched on this clock and on the subsequent clock.
LENGTH. Specifies the number of byte/words (depending on IF_CFG) to be transferred in
each burst cycle:
HOLD=0: Number of bytes/words = 2 ^ LENGTH
HOLD=1: Number of bytes/words = 2 ^ (LENGTH – 1)
Note: The maximum value of LENGTH is 10.
This 16-bit register controls the behavior of Mobile DiskOnChip P3 during
MultiBurst mode read cycles.
clock delay from CE#/OE# asserted until the first data word may be latched on D[15:0].
Bit 15
Bit 7
0
0
Bit 14
Bit 6
0
0
LENGTH
RFU_0
Bit 13
Bit 5
Data Sheet, Rev. 0.3
R
0
0
Bit 4
Description
12
0
0
R/W
Bit 11
Bit 3
0
0
HOLD
Bit 10
Bit 2
0
0
LATENCY
CLK_INV
Bit 1
Bit 9
R/W
0
0
Mobile DiskOnChip P3
93-SR-009-8L
BST_EN
Bit 0
Bit 8
0
0