HYB39S256800FE-7 Qimonda, HYB39S256800FE-7 Datasheet - Page 20

• Manufacturer Part Number: HYB39S256800FE-7
• Description: IC SDRAM 256MBIT 143MHZ 54TSOP
• Manufacturer: Qimonda

Specifications of HYB39S256800FE-7

• Format - Memory: RAM
• Memory Type: SDRAM
• Memory Size: 256M (32M x 8)
• Speed: 143MHz
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 54-TSOP II
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 675-1003-2

1)
2) For proper power-up see the operation section of this data sheet.
3) AC timing tests for LV-TTL versions have
4) If clock rising time is longer than 1 ns, a time (t
5) Access time from clock
6) If
7) These parameter account for the number of clock cycles and depend on the operating frequency of the clock, as follows:the number of
8) It is recommended to use two clock cycles between the last data-in and the precharge command in case of a write command without Auto-
9) When a Write command with Auto Precharge has been issued, a time of
Rev. 1.42, 2007-09
03292006-TMTK-JFEU
Parameter
Write Cycle
Last Data Input to Precharge
(Write without Auto Precharge)
Last Data Input to Activate(Write with Auto Precharge)
DQM Write Mask Latency
T
time is measured between
Specified
rate between 0.8 V and 2.0 V.
components with no termination and 0 pF load.
clock cycles = specified value of timing period (counted in fractions as a whole number)
Precharge. One clock cycle between the last data-in and the precharge command is also supported, but restricted to cycle times
or equal the specified
be applied. For each of the terms, if not already an integer, round up to the next highest integer.
A
t
T
= 0 to 70 °C;
is longer than 1 ns, a time (
t
AC
and
V
t
SS
OH
C L O C K
IN P U T
O U T P U T
= 0 V;
parameters are measured with a 50 pF only, without any resistive termination and with an input signal of 1V / ns edge
t
WR
t
ac
value, where
t
is 4.6 ns for PC133 components with no termination and 0 pF load,Data out hold time
IS
V
V
IH
DD
1 .4 V
,
and
t
T
V
DDQ
- 1) ns has to be added to this parameter.
V
t
t
IH
L Z
IL
= 3.3 V ± 0.3 V,
. All AC measurements assume
t
A C
t
ck
V
is equal to the actual system clock time.
IL
1 .4 V
= 0.4 V and
t
C L
T
/2 - 0.5) ns has to be added to this parameter.
t
t
O H
C H
t
T
t
T
t
t
A C
H Z
V
= 1 ns
IH
2 .4 V
0 .4 V
Symbol
t
t
t
WR
DAL(min.)
DQW
= 2.4 V with the timing referenced to the 1.4 V crossover point. The transition
IO.vsd
20
1.4 V
t
T
= 1 ns with the AC output load circuit shown in figure below.
t
Min.
14
0
DAL(min)
PC143–333
has be fullfilled before the next Activate Command can
–7
Max.
—
—
Measurement conditions for
Measurement conditions for
I/O
HY[B/I]39S256[40/80/16][0/7]F[E/T/F](L)
t
AC
Min.
12
0
t
CK
and
PC166–333
is equal to the actual system clock time.
256-MBit Synchronous DRAM
t
50 pF
OH
–6
Max.
—
—
Internet Data Sheet
t
oh
ns
t
t
CK
CK
Unit
is 1.8 ns for PC133
FIGURE 5
t
AC
Note
8)
9)
and
t
ck
1)2)3)
greater
t
OH