IC EEPROM 2KBIT 1MHZ 8SOIC

 

CAT93C56WI-GT3

Manufacturer Part NumberCAT93C56WI-GT3
DescriptionIC EEPROM 2KBIT 1MHZ 8SOIC
ManufacturerON Semiconductor
CAT93C56WI-GT3 datasheets

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Specifications of CAT93C56WI-GT3

Format - MemoryEEPROMs - SerialMemory TypeEEPROM
Memory Size2K (256 x 8 or 128 x 16)Speed1MHz
InterfaceMicrowire, 3-Wire SerialVoltage - Supply1.8 V ~ 5.5 V
Operating Temperature-40°C ~ 85°CPackage / Case8-SOIC (3.9mm Width)
Lead Free Status / RoHS StatusLead free / RoHS CompliantOther namesCAT93C56WI-GT3CT
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CAT93C56, CAT93C57
2-Kb Microwire Serial
CMOS EEPROM
Description
The CAT93C56/57 is a 2−kb CMOS Serial EEPROM device which
is organized as either 128 registers of 16 bits (ORG pin at V
registers of 8 bits (ORG pin at GND). Each register can be written (or
read) serially by using the DI (or DO) pin. The CAT93C56/57 features
sequential read and self−timed internal write with auto−clear. On−chip
Power−On Reset circuitry protects the internal logic against powering
up in the wrong state.
Features
•
High Speed Operation: 2 MHz
•
1.8 V to 5.5 V Supply Voltage Range
•
Selectable x8 or x16 Memory Organization
•
Sequential Read
•
Software Write Protection
•
Power−up Inadvertant Write Protection
•
Low Power CMOS Technology
•
1,000,000 Program/Erase Cycles
•
100 Year Data Retention
•
Industrial and Extended Temperature Ranges
•
8−pin PDIP, SOIC, TSSOP and 8−pad TDFN Packages
•
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
V
CC
ORG
CS
CAT93C56
CAT93C57
SK
DI
GND
Figure 1. Functional Symbol
NOTE: When the ORG pin is connected to V
When it is connected to ground, the x8 pin is selected. If the ORG pin is left
unconnected, then an internal pullup device will select the x16 organization.
© Semiconductor Components Industries, LLC, 2009
August, 2009 − Rev. 18
) or 256
CC
DO
, the x16 organization is selected.
CC
1
http://onsemi.com
SOIC−8
SOIC−8 EIAJ
TDFN−8
V or W SUFFIX
X SUFFIX
VP2 SUFFIX
CASE 751BD
CASE 751BE
CASE 511AK
PDIP−8
TDFN−8
TSSOP−8
L SUFFIX
ZD4 SUFFIX
Y SUFFIX
CASE 646AA
CASE 511AL
CASE 948AL
PIN CONFIGURATIONS
1
V
CS
CC
SK
NC
DI
ORG
DO
GND
PDIP (L), SOIC (V, X),
TSSOP (Y), TDFN (VP2, ZD4*)
NC
ORG
* TDFN 3x3 mm (ZD4) and
1
SOIC (W) rotated pin−out
V
GND
CC
packages are available for
CS
DO
CAT93C57 and CAT93C56,
SK
DI
Rev. E only (not recommen-
SOIC (W*)
ded for new designs of
CAT93C56)
(Top Views)
PIN FUNCTION
Pin Name
Function
CS
Chip Select
SK
Clock Input
DI
Serial Data Input
DO
Serial Data Output
V
Power Supply
CC
GND
Ground
ORG
Memory Organization
NC
No Connection
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 16 of this data sheet.
Publication Order Number:
CAT93C56/D

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CAT93C56WI-GT3 Summary of contents

  • Page 1

    ... Power−On Reset circuitry protects the internal logic against powering up in the wrong state. Features • High Speed Operation: 2 MHz • 1 5.5 V Supply Voltage Range • Selectable x8 or x16 Memory Organization • Sequential Read • Software Write Protection • Power−up Inadvertant Write Protection • ...

  • Page 2

    Table 1. ABSOLUTE MAXIMUM RATINGS Parameters Storage Temperature Voltage on Any Pin with Respect to Ground (Note 1) Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is ...

  • Page 3

    Table 4. D.C. OPERATING CHARACTERISTICS, CAT93C56/57, Die Rev. E – Mature Product (CAT93C56, Rev. E – NOT RECOMMENDED FOR NEW DESIGNS) Symbol Parameter I Power Supply Current (Write) CC1 I Power Supply Current (Read) CC2 I Power Supply Current (Standby) ...

  • Page 4

    Table 6. A.C. CHARACTERISTICS (V = +1.8V to +5.5V −40°C to +125°C, unless otherwise specified Symbol t CS Setup Time CSS t CS Hold Time CSH t DI Setup Time DIS t DI Hold Time DIH ...

  • Page 5

    ... Input Pulse Voltages Timing Reference Voltages Output Load Device Operation The CAT93C56/ 2048−bit nonvolatile memory intended for use with industry standard microprocessors. The CAT93C56/57 can be organized as either registers of 16 bits or 8 bits. When organized as X16, seven 10−bit instructions for 93C57 or seven 11−bit instructions for 93C56 control the reading, writing and erase operations of the device. When organized as X8, seven 11− ...

  • Page 6

    The format for all instructions sent to the device is a logical “1” start bit, a 2−bit (or 4−bit) opcode, 7−bit address (CAT93C57) / 8−bit address (CAT93C56) (an additional bit Table 10. INSTRUCTION SET Start Bit Instruction Device Type READ ...

  • Page 7

    Read Upon receiving a READ command and an address (clocked into the DI pin), the DO pin of the CAT93C56/57 will come out of the high impedance state and, after sending an initial dummy zero bit, will begin shifting out ...

  • Page 8

    ... The ready/busy status of the CAT93C56/57 can be determined by selecting the device and polling the DO pin. Since this device features Auto−Clear before write NOT necessary to erase a memory location before it is written into ...

  • Page 9

    ... The clocking of the SK pin is not necessary after the device has entered the self clocking mode. The ready/busy status of the CAT93C56/57 can be determined by selecting the device and polling the DO pin not necessary for all memory locations to be cleared before the WRAL command is executed. ...

  • Page 10

    PIN # 1 IDENTIFICATION D TOP VIEW SIDE VIEW Notes: (1) All dimensions are in millimeters. (2) Complies with JEDEC MS-001. PACKAGE DIMENSIONS PDIP−8, 300 mils CASE 646AA−01 ISSUE A SYMBOL ...

  • Page 11

    PIN # 1 IDENTIFICATION TOP VIEW SIDE VIEW Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MS-012. PACKAGE DIMENSIONS SOIC 8, 150 mils CASE 751BD−01 ISSUE O SYMBOL ...

  • Page 12

    PIN#1 IDENTIFICATION TOP VIEW SIDE VIEW Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with EIAJ EDR-7320. PACKAGE DIMENSIONS SOIC−8, 208 mils CASE 751BE−01 ISSUE O SYMBOL ...

  • Page 13

    E1 e TOP VIEW SIDE VIEW Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MO-153. PACKAGE DIMENSIONS TSSOP8, 4.4x3 CASE 948AL−01 ISSUE O SYMBOL MIN A A1 0.05 A2 ...

  • Page 14

    D E PIN#1 INDEX AREA TOP VIEW SYMBOL MIN NOM A 0.70 0.75 A1 0.00 0.02 A2 0.45 0.55 A3 0.20 REF b 0.20 0.25 D 1.90 2.00 D2 1.30 1.40 E 2.90 3.00 E2 1.20 1.30 e 0.50 TYP ...

  • Page 15

    D PIN#1 INDEX AREA TOP VIEW SYMBOL MIN NOM A 0.70 0.75 A1 0.00 0.02 A3 0.20 REF b 0.23 0.30 D 2.90 3.00 D2 2.20 −−− E 2.90 3.00 E2 1.40 −−− e 0.65 TYP L 0.20 0.30 Notes: ...

  • Page 16

    ... For SOIC, EIAJ (X) package the standard lead finish is Matte−Tin. This package is available in 2,000 pcs/reel, i.e. CAT93C56XI−T2. 15. For additional package and temperature options, please contact your nearest ON Semiconductor sales office. 16. For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D ...

  • Page 17

    ... Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303− ...

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