MD2534-D2G-X-P SanDisk, MD2534-D2G-X-P Datasheet - Page 60

• Manufacturer Part Number: MD2534-D2G-X-P
• Description: IC MDOC H3 2GB FBGA
• Manufacturer: SanDisk

Specifications of MD2534-D2G-X-P

• Format - Memory: FLASH
• Memory Type: FLASH - Nand
• Memory Size: 2G (256M x 8)
• Interface: Parallel
• Voltage - Supply: 1.65 V ~ 1.95 V, 2.5 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 115-TFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Speed: -

mDOC H3 will interrupt the host system in the following cases:
• On completion of block device operation to mDOC H3.
• Device is ready to send a data block during a read operation.
• Device is ready to receive a data block (excluding the first) during write operation.
The device will exit the interrupt-pending state in the following cases:
• The Device Status register is read, and BSY bit is cleared;
• Both BSY and DRQ bits in Device Status register are cleared, and the Command register is
• SRST bit in Device Control register is set.
9.8
mDOC H3 enhances performance using various proprietary techniques among them are
• Burst operation to read large chunks of data, providing a Burst read speed.
• DMA operation to release the CPU for other tasks in coordination with the platform’s DMA
9.8.1 DMA Operation
mDOC H3 provides a DMARQ# output that enables data transfer using the host DMA controller.
During DMA operation, the DMARQ# output is used to notify the host DMA controller that data
is ready to be read or written. mDOC H3 protocol enables such data transfer up to the maximal
size of 128KB per read or write operation.
The DMARQ# output sensitivity is selected by setting the EDGE bit in the DMA Control
register:
1.
2. Level DMARQ# output is asserted while the data is available for read, or data can be
The following steps are required in order to initiate a DMA operation:
1.
2.
3. Enable DMA transfer with DMA_EN bit in the DMA control register.
60
written.
controller. This is especially useful during the boot stage. Up to 128KB of data can be
transferred during a DMA operation.
Edge DMARQ# output pulses to indicate to the DMA controller that a data is ready to be
transferred. The EDGE bit is set to 1 for this mode. The amount of data that will be
transferred corresponds to data block size.
accepted for write. The EDGE bit is set to 0 for this mode.
If the DMA controller supports an edge-sensitive DMARQ# signal, then initialize the DMA
controller to transfer 512 bytes (or your chosen data block size) upon each DMA request. If
the DMA controller supports a level-sensitive DMARQ# signal, then initialize the DMA
controller to transfer data continuously while DMARQ# is asserted.
Set in the DMA Control register values of EDGE bit, PULSE_WIDTH and DMA polarity
corresponding to settings of the host DMA controller. This can be done only once after
system power-up.
DMA and Burst Operation
Data Sheet (Preliminary) Rev. 0.2
mDOC H3 Embedded Flash Drive
92-DS-1205-10