CAT93C46RVI-GT3 ON Semiconductor, CAT93C46RVI-GT3 Datasheet
CAT93C46RVI-GT3
Specifications of CAT93C46RVI-GT3
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CAT93C46RVI-GT3 Summary of contents
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... CAT93C46R SK DI GND Figure 1. Functional Symbol *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. © Semiconductor Components Industries, LLC, 2009 October, 2009 − Rev. 7 CASE 646AA SOIC−8 V SUFFIX ...
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Table 1. ABSOLUTE MAXIMUM RATINGS Parameter Storage Temperature Voltage on Any Pin with Respect to Ground (Note 1) Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is ...
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Table 4. PIN CAPACITANCE Symbol C (Note 4) Output Capacitance (DO) OUT C (Note 4) Input Capacitance (CS, SK, DI, ORG These parameters are tested initially and after a design or process change that affects the parameter according ...
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... WRAL 1 00 Device Operation The CAT93C46R is a 1024−bit nonvolatile memory intended for use with industry standard microprocessors. The CAT93C46R can be organized as either registers of 16 bits or 8 bits. When organized as X16, seven 9−bit instructions control the reading, writing and erase operations of the device. When organized as X8, seven 10− ...
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SK t VALID DI t CSS HIGH− HIGH− SKHI SKLOW DIS VALID t DIS ...
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... SK pin is not necessary after the device has entered the self clocking mode. The ready/busy status of the CAT93C46R can be determined by selecting the device and polling the DO pin not necessary for all memory locations to be cleared before the WRAL command is executed. ...
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HIGH− N− HIGH−Z Figure 7. Erase Instruction Timing 0 t ...
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PIN # 1 IDENTIFICATION D TOP VIEW SIDE VIEW Notes: (1) All dimensions are in millimeters. (2) Complies with JEDEC MS-001. PACKAGE DIMENSIONS PDIP−8, 300 mils CASE 646AA−01 ISSUE A SYMBOL ...
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PIN # 1 IDENTIFICATION TOP VIEW SIDE VIEW Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MS-012. PACKAGE DIMENSIONS SOIC 8, 150 mils CASE 751BD−01 ISSUE O SYMBOL ...
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PIN#1 IDENTIFICATION TOP VIEW SIDE VIEW Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with EIAJ EDR-7320. PACKAGE DIMENSIONS SOIC−8, 208 mils CASE 751BE−01 ISSUE O SYMBOL ...
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E1 e TOP VIEW SIDE VIEW Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MO-153. PACKAGE DIMENSIONS TSSOP8, 4.4x3 CASE 948AL−01 ISSUE O SYMBOL MIN A A1 0.05 A2 ...
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D E PIN#1 INDEX AREA TOP VIEW SYMBOL MIN NOM A 0.70 0.75 A1 0.00 0.02 A2 0.45 0.55 A3 0.20 REF b 0.20 0.25 D 1.90 2.00 D2 1.30 1.40 E 2.90 3.00 E2 1.20 1.30 e 0.50 TYP ...
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... CAT93C46RXI−T2 CAT93C46RYI−GT3 CAT93C46RVP2IGT3 (Note 13) 8. The device used in the above example is a CAT93C46RVI−GT3 (SOIC, Industrial Temperature, NiPdAu, Tape & Reel). 9. All packages are RoHS−compliant (Lead−free, Halogen−free). 10. The standard lead finish is NiPdAu. 11. For SOIC, EIAJ (X) package the standard lead finish is Matte−Tin. This package is available in 2,000 pcs/reel, i.e. CAT93C46RXI−T2. ...