CAT93C66XI ON Semiconductor, CAT93C66XI Datasheet

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... Power−On Reset circuitry protects the internal logic against powering up in the wrong state. Features • High Speed Operation: 2 MHz • 1 5.5 V Supply Voltage Range • Selectable x8 or x16 Memory Organization • Sequential Read • Software Write Protection • Power−up Inadvertent Write Protection • ...

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MARKING DIAGRAMS A = Assembly Location Code 3 = Mark “3” for (lead finish Matte−Tin) A3G G = Product Revision: Fixed as “G” 93C66XT 93C66X = Specific Device Code YMXXXX T = Temperature Range Y = Production Year (Last Digit) ...

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... V ≤ V < 4 1.8 V ≤ V < 4 −100 http://onsemi.com 3 Function V Power Supply CC GND Ground Memory Organization NC No Connection Ratings −65 to +150 −0.5 to +6.5 + 0.5 V. During transitions, the voltage on any pin may Min Units 1,000,000 Program / Erase Cycles 100 Years Min Max 1 500 2 ...

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Table 5. PIN CAPACITANCE (T = 25° 1.0 MHz Symbol C (Note 4) Output Capacitance (DO) OUT C (Note 4) Input Capacitance (CS, SK, DI, ORG These parameters are tested initially and after a ...

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... V Output Load Current Source I Device Operation The CAT93C66 is a 4096−bit nonvolatile memory intended for use with industry standard microprocessors. The CAT93C66 can be organized as either registers of 16 bits or 8 bits. When organized as X16, seven 11−bit instructions control the reading, writing and erase operations of the device. When organized as X8, seven 12− ...

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Read Upon receiving a READ command and an address (clocked into the DI pin), the DO pin of the CAT93C66 will come out of the high impedance state and, after sending an initial dummy zero bit, will begin shifting out ...

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... The falling edge of CS will start the CSMIN self clocking clear and data store cycle of the memory location specified in the instruction. The clocking of the SK pin is not necessary after the device has entered the self clocking mode. The ready/busy status of the CAT93C66 can be determined by selecting the device and polling the DO pin. Since this device features Auto− ...

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... The clocking of the SK pin is not necessary after the device has entered the self clocking mode. The ready/busy status of the CAT93C66 can be determined by selecting the device and polling the DO pin not necessary for all memory locations to be cleared before the WRAL command is executed. ...

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PIN # 1 IDENTIFICATION D TOP VIEW SIDE VIEW Notes: (1) All dimensions are in millimeters. (2) Complies with JEDEC MS-001. PACKAGE DIMENSIONS PDIP−8, 300 mils CASE 646AA−01 ISSUE A SYMBOL ...

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PIN # 1 IDENTIFICATION TOP VIEW SIDE VIEW Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MS-012. PACKAGE DIMENSIONS SOIC 8, 150 mils CASE 751BD−01 ISSUE O SYMBOL ...

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PIN#1 IDENTIFICATION TOP VIEW SIDE VIEW Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with EIAJ EDR-7320. PACKAGE DIMENSIONS SOIC−8, 208 mils CASE 751BE−01 ISSUE O SYMBOL ...

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E1 e TOP VIEW SIDE VIEW Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MO-153. PACKAGE DIMENSIONS TSSOP8, 4.4x3 CASE 948AL−01 ISSUE O SYMBOL MIN A A1 0.05 A2 ...

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D E PIN#1 INDEX AREA TOP VIEW SYMBOL MIN NOM A 0.70 0.75 A1 0.00 0.02 A2 0.45 0.55 A3 0.20 REF b 0.20 0.25 D 1.90 2.00 D2 1.30 1.40 E 2.90 3.00 E2 1.20 1.30 e 0.50 TYP ...

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D e PIN #1 IDENTIFICATION TOP VIEW θ1 b θ2 SIDE VIEW Notes: (1) All dimensions in millimeters. Angles in degrees. (2) Complies with JEDEC standard MO-178. PACKAGE DIMENSIONS SOT−23, 6 Lead CASE 527AJ−01 ISSUE O SYMBOL ...

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... The device used in the above example is a CAT93C66VI−GT3 (SOIC, Industrial Temperature, NiPdAu, Tape & Reel, 3,000 units/Reel). 12. For SOIC, EIAJ (X) package the standard lead finish is Matte−Tin. This package is available in 2,000 pcs/reel, i.e. CAT93C66XI−T2. 13. For additional package and temperature options, please contact your nearest ON Semiconductor Sales office. ...