EPC2LI20N

... Easy-to-use 4-pin interface to Altera FPGAs ■ Low current during configuration and near-zero standby current ■ 5.0-V and 3.3-V operation Programming support with the Altera Programming Unit (APU) and ■ programming hardware from Data I/O, BP Microsystems, and other third-party programmers ■ Available in compact plastic packages 8-pin plastic dual in-line package (PDIP) ■ ...

... Functional Description With SRAM-based devices, configuration data must be reloaded each time the device powers up, the system initializes, or when new configuration data is needed. Altera configuration devices store configuration data for SRAM-based ACEX 1K, APEX 20K, APEX II, Arria GX, Cyclone, Cyclone II, FLEX 10K, FLEX 6000, Mercury, Stratix, Stratix GX, Stratix II, and Stratix II GX devices ...

... EP2C70 FLEX 10K EPF10K10 EPF10K20 EPF10K30 EPF10K40 EPF10K50 EPF10K70 EPF10K100 FLEX 10KA EPF10K10A EPF10K30A EPF10K50V EPF10K100A EPF10K130V EPF10K250A © December 2009 Altera Corporation Data Size (Bits) EPC1064/ (1) 1064V EPC1213 354,832 — — 648,016 — — 1,008,016 — — 1,524,016 — — ...

... December 2009 Altera Corporation ...

... DCLK nCS OE Notes to Figure 4–1: (1) The EPC1441 devices do not support data cascading. The EPC1, EPC2, and EPC1213 devices support data cascading. (2) The OE pin is a bidirectional open-drain pin. © December 2009 Altera Corporation Data Size (Bits) EPC1064/ (1) 1064V EPC1213 5,000,000 — — ...

... Altera FPGA. For specific details about configuration interface connections, including pull-up resistor values, supply voltages and MSEL pin setting, refer to the appropriate FPGA family chapter in the Handbook. Figure 4–2. Altera FPGA Configured Using an EPC1, EPC2, or EPC1441 Configuration Device FPGA CONF_DONE n ...

... DATA, and OE) are connected to every device in the chain. Figure 4–3 shows the basic configuration interface connections between a configuration device chain and the Altera FPGA. f For specific details about configuration interface connections, including pull-up resistor values, supply voltages and MSEL pin setting, refer to the appropriate FPGA family chapter in the © ...

... Configuration Devices for SRAM-Based LUT Devices Data Sheet Figure 4–3. Altera FPGA Configured Using Two EPC1 or EPC2 Configuration Devices ...

... MAX+PLUS II software’s Global Project Device Options dialog box (Assign menu). f For more information about FPGA configuration and configuration interface connections between configuration devices and Altera FPGAs, refer to the appropriate FPGA family chapter in the Power and Operation This section describes Power-On Reset (POR) delay, error detection, and 3.3-V and 5 ...

... This low signal on nSTATUS will drive the OE pin of the configuration device low, which will reset the configuration device. CRC checking is performed when configuring all Altera FPGAs. 3.3-V or 5.0-V Operation The EPC1, EPC2, and EPC 1441 configuration device may be powered at 3 ...

... CONF_DONE pull-up resistors must be connected to 3 these configuration devices are powered at 5.0 V, the nSTATUS and CONF_DONE pull-up resistors can be connected to 3 5.0 V. © December 2009 Altera Corporation , while a low logic level means the pin should be CC VPP Voltage Level VCCSEL Pin Logic (V) 3 ...

... Configuration Devices for SRAM-Based LUT Devices Data Sheet Programming and Configuration File Support The Quartus II and MAX+PLUS II softwares provide programming support for Altera configuration devices. During compilation, the Quartus II and MAX+PLUS II softwares automatically generates a ...

... Device EPC2 EPC1 EPC1441 The following steps explain how to program Altera configuration devices using the Quartus II software and the APU: 1. Choose the Quartus II Programmer (Tools menu). 2. Load the appropriate .pof by clicking Add. The Device column displays the device for the current programming file. ...

... These instructions are used when programming an EPC2 device via JTAG ports with a USB Blaster, MasterBlaster, ByteBlaster II, EthernetBlaster, or ByteBlaster MV download cable, or using a .jam, .jbc, or .svf via an embedded processor. Application Note 39 (IEEE 1149.1 (JTAG) Boundary-Scan or the EPC2 BSDL files on the Altera web site. .pof , .jam, .jbc) in © December 2009 Altera Corporation ...

... Capture register setup time JSSU t Capture register hold time JSH t Update register clock to output JSCO t Update register high-impedance to valid JSZX output t Update register valid output to high JSXZ impedance © December 2009 Altera Corporation t JCP JCH JCL JPSU t t JPZX JPCO t t JSSU ...

... MHz 40 65 100 100 ns 40 — — — — ns — — — — 100 — — ns — — — — © December 2009 Altera Corporation ...

... DCLK frequency CLK t DCLK high time for the first device in the configuration MCH chain t DCLK low time for the first device in the configuration MCL chain © December 2009 Altera Corporation Min Typ Max — — 200 — — 80 — — 300 30 — ...

... December 2009 Timing Information Max Units — ns — — EPC1 Max Unit — ns — ns — ns — — MHz — ns — — 100 ns Altera Corporation ...

... CMOS output voltage V Low-level output voltage OL I Input leakage current I I Tri-state output off-state current OZ © December 2009 Altera Corporation Table 4–19 provide information about absolute maximum ratings, (Note 1) Conditions With respect to ground (2) With respect to ground (2) — — — ...

... Table 4–19: (1) For more information, refer to the Operating Requirements for Altera Devices Data Sheet. (2) The minimum DC input is -0.3 V. During transitions, the inputs may undershoot to -2 overshoot to 7.0 V for input currents less than 100 mA and periods shorter than 20 ns under no-load conditions. ...

... DATA 2 4 DCLK © December 2009 Altera Corporation 32-Pin TQFP (2) Pin Type 31 Output Serial data output. The DATA pin connects to the DATA0 of the FPGA. DATA is latched into the FPGA on the rising edge of DCLK. The DATA pin is tri-stated before configuration and when the nCS pin is high ...

... JTAG data input pin. Connect this pin to V JTAG circuitry is not used. This pin is only available in EPC2 devices. 28 Output JTAG data output pin. Do not connect this pin if the JTAG circuitry is not used. This pin is only available in EPC2 devices. Pin Information Description if the CC © December 2009 Altera Corporation ...

... Notes to Table 4–20: (1) This package is available for EPC1 and EPC1441 devices only. (2) This package is available for EPC2 and EPC1441 devices only. © December 2009 Altera Corporation 32-Pin TQFP (2) Pin Type 25 Input JTAG mode select pin. Connect this pin to V JTAG circuitry is not used. ...

... Package (Note N.C. N. VCC 2 22 N.C. N. N.C. N. N.C. N. N.C. N. N. 32-Pin TQFP EPC1441 EPC1064 EPC1064V nCASC is a reserved pin and should N.C. VPP 23 N.C. 22 N.C. 21 N.C. 20 N.C. 19 N.C. 18 VPPSEL Altera Device Package Information © December 2009 Altera Corporation ...

... April 2007 2.2 ■ July 2004 2.0 ■ September 2003 1.0 ■ © December 2009 Altera Corporation Package Temperature 32-pin TQFP 32-pin TQFP 20-pin PLCC 20-pin PLCC 20-pin PLCC 20-pin PLCC 8-pin PDIP 8-pin PDIP 32-pin TQFP 32-pin TQFP ...

... Configuration Devices for SRAM-Based LUT Devices Data Sheet Configuration Handbook (Complete Two-Volume Set) Chapter Revision History © December 2009 Altera Corporation ...