AT17LV010-10JU | |
|---|---|
| Manufacturer Part Number | AT17LV010-10JU |
| Description | IC SRL CONFIG EEPROM 1M 20-PLCC |
| Manufacturer | Atmel |
| AT17LV010-10JU datasheets |
|
Availability: By request
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Warranty: 60 days
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Specifications of AT17LV010-10JU | |||
|---|---|---|---|
| Programmable Type | Serial EEPROM | Memory Size | 1Mb |
| Voltage - Supply | 3 V ~ 3.6 V | Operating Temperature | -40°C ~ 85°C |
| Package / Case | 20-LCC (J-Lead) | Organization | 1 M x 1 |
| Interface Type | 2-Wire | Maximum Clock Frequency | 15 MHz |
| Supply Voltage (max) | 5 V | Supply Voltage (min) | 3.3 V |
| Maximum Operating Current | 200 uA | Maximum Operating Temperature | + 85 C |
| Mounting Style | SMD/SMT | Minimum Operating Temperature | - 40 C |
| Operating Supply Voltage | 3.3 V, 5 V | For Use With | ATDH2225 - CABLE ISP FOR AT17ATDH2200E - CONFIGURATOR PROGRAM BOARD KIT |
| Lead Free Status / RoHS Status | Lead free / RoHS Compliant | ||
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3. Device Description
The control signals for the configuration EEPROM (CE, RESET/OE and CCLK) interface directly
with the FPGA device control signals. All FPGA devices can control the entire configuration pro-
cess and retrieve data from the configuration EEPROM without requiring an external intelligent
controller.
The configuration EEPROM RESET/OE and CE pins control the tri-state buffer on the DATA
output pin and enable the address counter. When RESET/OE is driven High, the configuration
EEPROM resets its address counter and tri-states its DATA pin. The CE pin also controls the
output of the AT17LV series configurator. If CE is held High after the RESET/OE reset pulse, the
counter is disabled and the DATA output pin is tri-stated. When OE is subsequently driven Low,
the counter and the DATA output pin are enabled. When RESET/OE is driven High again, the
address counter is reset and the DATA output pin is tri-stated, regardless of the state of CE.
When the configurator has driven out all of its data and CEO is driven Low, the device tri-states
the DATA pin to avoid contention with other configurators. Upon power-up, the address counter
is automatically reset.
This is the default setting for the device. Since almost all FPGAs use RESET Low and OE High,
this document will describe RESET/OE.
4. Pin Description
AT17LV65/
AT17LV128/
AT17LV256
8
DIP/
LAP/
20
Name
I/O
SOIC
PLCC
DATA
I/O
1
2
CLK
I
2
4
WP1
I
–
–
RESET/OE
I
3
6
WP2
I
CE
I
4
8
GND
5
10
CEO
O
6
14
A2
I
READY
O
–
–
SER_EN
I
7
17
V
8
20
CC
Note:
1. The CEO feature is not available on the AT17LV65 device.
AT17LV65/128/256/512/010/002/040
6
AT17LV512/
AT17LV010
8
20
DIP/
20
20
SOIC
LAP
PLCC
SOIC
2
1
2
1
4
2
4
3
–
–
5
–
6
3
6
8
–
7
–
8
4
8
10
10
5
10
11
13
14
6
14
–
–
–
15
–
17
7
17
18
20
8
20
20
AT17LV002
8
DIP/
LAP/
20
20
44
SOIC
PLCC
SOIC
TQFP
1
2
1
40
2
4
3
43
–
5
–
–
3
6
8
13
–
7
–
–
4
8
10
15
5
10
11
18
13
6
14
21
–
–
15
–
23
7
17
18
35
8
20
20
38
2321I–CNFG–2/08
AT17LV040
44
TQFP
40
43
–
13
–
15
18
21
23
35
38
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|
|
AT17LV010-10PI |
IC SRL CONFIG EEPROM 1M 8-DIP | Atmel |
|
|
AT17LV010A-10QC |
IC CONFIG SEEPROM 1M 3.3V 32TQFP | Atmel |
|
