IC SRL CONFIG EEPROM 1M 20-PLCC

 

AT17LV010-10JU

Manufacturer Part NumberAT17LV010-10JU
DescriptionIC SRL CONFIG EEPROM 1M 20-PLCC
ManufacturerAtmel
AT17LV010-10JU datasheets

Availability: By request

International delivery:

Warranty: 60 days

Shipping & payment terms

Added to cart

Select quantity

 

Specifications of AT17LV010-10JU

Programmable TypeSerial EEPROMMemory Size1Mb
Voltage - Supply3 V ~ 3.6 VOperating Temperature-40°C ~ 85°C
Package / Case20-LCC (J-Lead)Organization1 M x 1
Interface Type2-WireMaximum Clock Frequency15 MHz
Supply Voltage (max)5 VSupply Voltage (min)3.3 V
Maximum Operating Current200 uAMaximum Operating Temperature+ 85 C
Mounting StyleSMD/SMTMinimum Operating Temperature- 40 C
Operating Supply Voltage3.3 V, 5 VFor Use WithATDH2225 - CABLE ISP FOR AT17ATDH2200E - CONFIGURATOR PROGRAM BOARD KIT
Lead Free Status / RoHS StatusLead free / RoHS Compliant  
1
Page 1
2
Page 2
3
Page 3
4
Page 4
5
Page 5
6
Page 6
7
Page 7
8
Page 8
9
Page 9
10
Page 10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
Page 8/26

Download datasheet (617Kb)Embed
PrevNext
4.10
A2
Device selection input, A2. This is used to enable (or select) the device during programming
(i.e., when SER_EN is Low). A2 has an internal pull-down resistor.
4.11
READY
Open collector reset state indicator. Driven Low during power-up reset, released when power-up
is complete. It is recommended to use a 4.7 kΩ pull-up resistor when this pin is used.
4.12
SER_EN
Serial enable must be held High during FPGA loading operations. Bringing SER_EN Low
enables the Two-Wire Serial Programming Mode. For non-ISP applications, SER_EN should be
tied to V
4.13
V
CC
3.3V (±10%) and 5.0V (±5% Commercial, ±10% Industrial) power supply pin.
5. FPGA Master Serial Mode Summary
The I/O and logic functions of any SRAM-based FPGA are established by a configuration pro-
gram. The program is loaded either automatically upon power-up, or on command, depending
on the state of the FPGA mode pins. In Master mode, the FPGA automatically loads the config-
uration program from an external memory. The AT17LV Serial Configuration EEPROM has
been designed for compatibility with the Master Serial mode.
This document discusses the Atmel AT40K, AT40KAL and AT94KAL applications as well as Xil-
inx applications.
6. Control of Configuration
Most connections between the FPGA device and the AT17LV Serial EEPROM are simple and
self-explanatory.
• The DATA output of the AT17LV series configurator drives DIN of the FPGA devices.
• The master FPGA CCLK output drives the CLK input of the AT17LV series configurator.
• The CEO output of any AT17LV series configurator drives the CE input of the next
configurator in a cascaded chain of EEPROMs.
• SER_EN must be connected to V
• The READY
driven Low while the device is in its power-on reset cycle and released (tri-stated) when the
cycle is complete.
Note:
AT17LV65/128/256/512/010/002/040
8
.
CC
(except during ISP).
CC
(1)
pin is available as an open-collector indicator of the device’s reset status; it is
1. This pin is not available for the AT17LV65/128/256 devices.
2321I–CNFG–2/08

Related parts for AT17LV010-10JU

Part Number DescriptionManufacturer Datasheet
  AT17LV010A ATMEL Corporation
  AT17LV01010JI PLCC20 ATMEL Corporation
  AT17LV01010JU PLCC ATMEL Corporation
  AT17LV01010PI DIP-8 ATMEL Corporation
  AT17LV010A10PC DIP8 ATMEL Corporation
AT17LV010A-10PC  AT17LV010A-10PC IC CONFIG SEEPROM 1M 3.3V 8DIP Atmel
AT17LV010A-10QI  AT17LV010A-10QI IC SRL CONFIG EEPROM 1M 32-TQFP Atmel
AT17LV010A-10PI  AT17LV010A-10PI IC CONFIG SEEPROM 1M 3.3V 8DIP Atmel
AT17LV010-10JI  AT17LV010-10JI IC SRL CONFIG EEPROM 1M 20-PLCC Atmel
AT17LV010A-10JU  AT17LV010A-10JU IC CONFIG SEEPROM 1M 3.3V 20PLCC Atmel
AT17LV010-10JC  AT17LV010-10JC IC SER CNFIG PROM 1M 3.3V 20PLCC Atmel
AT17LV010A-10JC  AT17LV010A-10JC IC CONFIG SEEPROM 1M 3.3V 20PLCC Atmel
AT17LV010A-10JI  AT17LV010A-10JI IC CONFIG SEEPROM 1M 3.3V 20PLCC Atmel
AT17LV010-10PI  AT17LV010-10PI IC SRL CONFIG EEPROM 1M 8-DIP Atmel
AT17LV010A-10QC  AT17LV010A-10QC IC CONFIG SEEPROM 1M 3.3V 32TQFP Atmel