XC17S100APD8C | |
|---|---|
| Manufacturer Part Number | XC17S100APD8C |
| Description | IC PROM SER 100000 C-TEMP 8-DIP |
| Manufacturer | Xilinx Inc |
| XC17S100APD8C datasheets |
|
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Specifications of XC17S100APD8C | |||
|---|---|---|---|
| Programmable Type | OTP | Memory Size | 1Mb |
| Voltage - Supply | 3 V ~ 3.6 V | Operating Temperature | 0°C ~ 70°C |
| Package / Case | 8-DIP (0.300", 7.62mm) | Capacitance, Input | 10 pF |
| Capacitance, Output | 10 pF | Current, Input, Leakage | ±10 μA |
| Current, Operating | 15 mA | Current, Output, Leakage | ±10 |
| Data Retention | 20 yrs. | Density | 781216 |
| Interface | Parallel Bus | Memory Type | PROM |
| Organization | 1M×8 | Package Type | PDIP |
| Temperature, Operating | 0 to +70 °C | Time, Address Setup | 25 |
| Time, Rise | 50 ms | Voltage, Input, High | 3.3 V |
| Voltage, Input, Low | 0.8 V | Voltage, Output, High | 2.4 V |
| Voltage, Output, Low | 0.4 V | Voltage, Supply | 3.3 V |
| Lead Free Status / RoHS Status | Contains lead / RoHS non-compliant | ||
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DS078 (v1.10) June 25, 2007
Features
Configuration one-time programmable (OTP) read-only
memory designed to store configuration bitstreams for
Spartan™-II/Spartan-IIE FPGA devices
Simple interface to the Spartan device
Programmable reset polarity (active High or active Low)
Low-power CMOS floating gate process
3.3V PROM
Introduction
The XC17S00A family of PROMs provide an easy-to-use,
cost-effective method for storing Spartan-II/Spartan-IIE
device configuration bitstreams.
When the Spartan device is in Master Serial mode, it
generates a configuration clock that drives the Spartan
PROM. A short access time after the rising clock edge, data
appears on the PROM DATA output pin that is connected to
the Spartan device D
pin. The Spartan device generates
IN
Spartan-II/IIE FPGA
XC2S15
XC2S30
XC2S50
XC2S100
XC2S150
XC2S200
XC2S50E
XC2S100E
(1)
XC2S150E
XC2S200E
XC2S300E
XC2S400E
XC2S600E
Notes:
1.
Due to the higher configuration bit requirements of the XC2S150E device, an XC17S200A PROM is required to configure this FPGA.
2.
See XC17V00 series configuration PROMs data sheet at:
© 2000-2002, 2005, 2007 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
PowerPC is a trademark of IBM, Inc. All other trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS078 (v1.10) June 25, 2007
Product Specification
0
Spartan-II/Spartan-IIE Family OTP
Configuration PROMs (XC17S00A)
0
5
Available in compact plastic 8-pin DIP, 8-pin VOIC,
20-pin SOIC, or 44-pin VQFP packages
Programming support by leading programmer
manufacturers
Design support using the Xilinx Alliance and
Foundation™ series software packages
Guaranteed 20-year life data retention
Pb-free (RoHS-compliant) packaging available
the appropriate number of clock pulses to complete the
configuration. Once configured, it disables the PROM.
When a Spartan device is in Slave Serial mode, the PROM
and the Spartan device must both be clocked by an
incoming signal.
For device programming, either the Xilinx Alliance or the
Spartan device design file into a standard HEX format which
is then transferred to most commercial PROM programmers.
Configuration Bits
197,696
336,768
559,200
781,216
1,040,096
1,335,840
630,048
863,840
1,134,496
1,442,016
1,875,648
2,693,440
3,961,632
http://direct.xilinx.com/bvdocs/publications/ds073.pdf
www.xilinx.com
Product Specification
Compatible Spartan-II/IIE PROM
XC17S15A
XC17S30A
XC17S50A
XC17S100A
XC17S150A
XC17S200A
XC17S50A
XC17S100A
XC17S200A
XC17S200A
XC17S300A
(2)
XC17V04
(2)
XC17V04
1
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XC17S100APD8C Summary of contents |
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