XC17V04PC20C

Manufacturer Part NumberXC17V04PC20C
DescriptionIC PROM SER 4MBIT 3.3V 20-PLCC
ManufacturerXilinx Inc
XC17V04PC20C datasheets

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Specifications of XC17V04PC20C

Programmable TypeOTPMemory Size4Mb
Voltage - Supply3 V ~ 3.6 VOperating Temperature0°C ~ 70°C
Package / Case20-LCC (J-Lead)Lead Free Status / RoHS StatusContains lead / RoHS non-compliant
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DS073 (v1.12) November 13, 2008
Features
•
One-time programmable (OTP) read-only memory
designed to store configuration bitstreams of
®
Xilinx
FPGA devices
•
Simple interface to the FPGA
•
Cascadable for storing longer or multiple bitstreams
•
Programmable reset polarity (active High or active
Low) for compatibility with different FPGA solutions
•
Low-power CMOS floating-gate process
•
3.3V supply voltage
•
Guaranteed 20 year life data retention
Description
Xilinx introduces the high-density XC17V00 family of
configuration PROMs which provide an easy-to-use, cost-
effective method for storing large Xilinx FPGA configuration
bitstreams. Initial devices in the 3.3V family are available in
16 Mb, 8 Mb, 4 Mb, 2 Mb, and 1 Mb densities. See
and
Figure 2
for simplified block diagrams of the XC17V00
family.
The XC17V00 PROM can configure a Xilinx FPGA using
the FPGA serial configuration mode interface. When the
FPGA is in Master Serial mode, it generates a configuration
clock that drives the PROM. A short access time after the
rising clock edge, data appears on the PROM DATA output
pin that is connected to the FPGA DIN pin. The FPGA
generates the appropriate number of clock pulses to
complete the configuration. Once configured, it disables the
PROM. When the FPGA is in Slave Serial mode, the PROM
and the FPGA must both be clocked by an incoming signal.
(1)
The XC17V08
and XC17V16 PROM can optionally
configure a Xilinx FPGA using the FPGA Parallel
1. Specific part number and package combinations have been discontinued. Refer to XCN07010. Discontinued part number and package combinations
remain in this data sheet for reference.
© Copyright 2000–2008 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and
other countries. All other trademarks are the property of their respective owners.
DS073 (v1.12) November 13, 2008
Product Specification
0
XC17V00 Series Configuration PROMs
0
8
•
Available in compact plastic packages: VQ44, PC44,
PC20, VO8, and SO20
•
Programming support by leading programmer
manufacturers
•
Design support using the ISE
ISE WebPACK™ software
•
Dual configuration modes for the XC17V16 and
XC17V08
♦
♦
(SelectMAP) configuration mode interface. When the FPGA
is in Master SelectMAP mode, the FPGA generates the
configuration clock that drives the PROM.
When the FPGA is in Slave SelectMAP mode, an external,
Figure 1
free-running oscillator generates the configuration clock
that drives the PROM and the FPGA. After the rising
configuration clock (CCLK) edge, data is available on the
PROMs DATA (D0-D7) pins. The data is clocked into the
FPGA on the following rising edge of the CCLK
Multiple PROMs can be concatenated by using the CEO
output to drive the CE input of the following device. The
clock inputs and the DATA outputs of all PROMs in this
chain are interconnected. All devices are compatible and
can be cascaded with other members of the family.
For device programming, either the Xilinx ISE Foundation or
ISE WebPACK software compiles the FPGA design file into
a standard Hex format, which is then transferred to most
commercial PROM programmers.
www.xilinx.com
Product Specification
(1)
®
Foundation™ and
(1)
devices
Serial slow/fast configuration (up to 20 Mb/s)
Parallel (up to 160 Mb/s at 20 MHz)
(Figure
3).
1

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XC17V04PC20C Summary of contents

  • Page 1

    R DS073 (v1.12) November 13, 2008 Features • One-time programmable (OTP) read-only memory designed to store configuration bitstreams of ® Xilinx FPGA devices • Simple interface to the FPGA • Cascadable for storing longer or multiple bitstreams • Programmable reset ...

  • Page 2

    R X-Ref Target - Figure 1 RESET OE/ RESET CLK Figure 1: Simplified Block Diagram for XC17V04, XC17V02 X-Ref Target - Figure RESET OE/ RESET CLK BUSY Figure 2: Simplified Block ...

  • Page 3

    R Pin Description DATA[0:7] The array data value corresponding to the internal address counter location is output on enabled DATA[0-7] output pin(s) when CE is active active, and the internal address counter has not incremented beyond its Terminal ...

  • Page 4

    R Table 1: Pinouts for XC17V16 and XC17V08 Pin Name 44-pin VQFP (VQ44 16, 17, 26, 36 Notes: 1. Specific part number and package combinations have been discontinued. Refer to XCN07010. Capacity Table ...

  • Page 5

    R Capacity Table 4: Device Capacities Devices Configuration Bits XC17V04 (1) XC17V02 XC17V01 Notes: 1. Specific part number and package combinations have been discontinued. Refer to XCN07010. Pinout Diagrams for XC17V04, XC17V02 and XC17V01 ...

  • Page 6

    PC20 5 NC Top View (See Notes OE/RESET 8 Notes: 1. XC1701 is available in these packages. 2. XC1702 and XC1704 are available in these packages. 3. Specific part number ...

  • Page 7

    R Controlling PROMs Connecting the FPGA device with the PROM. • The DATA output(s) of the PROM(s) drives the configuration data input(s) of the lead FPGA device. • The Master FPGA CCLK output drives the CLK input(s) of the PROM(s). ...

  • Page 8

    R Table 6: Truth Table for XC17V00 Control Inputs Control Inputs (1) RESET CE Inactive Low Active Low Inactive High Active High Notes: 1. The XC17V00 RESET input has programmable polarity terminal count, highest address value. DS073 ...

  • Page 9

    R X-Ref Target - Figure 3 DOUT V CC 4.7K FPGA (1) Modes DIN CCLK DONE INIT PROGRAM (Low Resets the Address Pointer) (1) For Mode pin connections, refer to the appropriate FPGA data sheet or user guide. (2) For ...

  • Page 10

    R Absolute Maximum Ratings Symbol V Supply voltage relative to GND CC V Supply voltage relative to GND PP V Input voltage relative to GND IN V Voltage applied to High-Z output TS T Storage temperature (ambient) STG T Junction ...

  • Page 11

    R AC Characteristics over Operating Condition for XC17V04, XC17V02, and XC17V01 X-Ref Target - Figure 4 CE RESET/OE CLK T CE DATA Notes: 1 The XC17V00 RESET/OE input polarity is programmable. The RESET/OE input is shown in the timing diagram ...

  • Page 12

    R AC Characteristics over Operating Condition for XC17V16 and XC17V08 X-Ref Target - Figure SCE (1) RESET/OE CLK DATA (2) BUSY Note: 1 The XC17V00 RESET/OE input polarity is programmable. The RESET/OE input ...

  • Page 13

    R AC Characteristics over Operating Condition When Cascading X-Ref Target - Figure 6 RESET/OE CE CLK DATA CEO Notes: 1 The XC17V00 RESET/OE input polarity is programmable. The RESET/OE input is shown in the timing diagram with active-high RESET polarity. ...

  • Page 14

    ... XC17V01 PC20 = 20-pin Plastic Leaded Chip Carrier SO20 = 20-pin Plastic Small Outline Package Notes: 1. Specific part number and package combinations have been discontinued. Refer to XCN07010. DS073 (v1.12) November 13, 2008 Product Specification XC17V04PC20C XC17V04PC44C XC17V04VQ44C XC17V04PC20I XC17V04PC44I XC17V04VQ44I XC17V16 PC44 C (1) www.xilinx.com ...

  • Page 15

    R Revision History The following table shows the revision history for this document. . Date Version 07/26/00 1.0 Initial Xilinx release. 10/09/00 1.1 Updated 20-pin PLCC Pinouts. 11/16/00 1.2 Updated pinouts for XC17V16 and XC17V08, I and C OUT 02/20/01 ...

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