AT17F080A-30JC

... Table 1-1. AT17FxxxA Series Packages Package 8-lead LAP 20-lead PLCC 32-lead TQFP ® ® FLEX , Excalibur Table 1-1. The AT17FxxxA Series Con- AT17F040A AT17F080A Yes Yes Yes Yes Yes Yes FPGA ™ ® , Stratix , Configuration Flash Memory AT17F040A AT17F080A 2823D–CNFG–2/08 ...

Pin Configuration PAGESEL1 RESET/OE AT17F040A/080A 2 8-lead LAP DATA 1 8 VCC DCLK 2 7 SER_EN RESET/ (A2) nCASC nCS 4 5 GND 20-lead PLCC DCLK PAGESEL1 7 15 ...

Block Diagram Power-on READY Reset PAGE_EN Config. Page PAGESEL0 Select PAGESEL1 Flash Memory 4. Device Description The control signals for the configuration memory device (nCS, RESET/OE and DCLK) interface directly with the FPGA device control signals. All FPGA devices ...

Pin Description Table 5-1. Name DATA DCLK PAGE_EN PAGESEL0 PAGESEL1 RESET/ nCS GND nCASC A2 READY SER_EN V CC (1) 5.1 DATA Three-state DATA output for FPGA configuration. Open-collector bi-directional pin for configura- tion programming. (1) 5.2 DCLK Three-state ...

... This pin has an internal 20 k pull-up resistor. 2. This pin has an internal 30 kΩ pull-down resistor. AT17F040A/080A Table 5-2. When AT17F080A (8 Mbits) 00000 – 1FFFFh 20000 – 3FFFFh 40000 – 5FFFFh 60000 – 7FFFFh 00000 – 7FFFFh and GND is recommended. ...

READY Open collector reset state indicator. Driven Low during power-up reset, released when power-up is complete. (recommended 4.7 kΩ pull-up on this pin if used). (1) 5.11 SER_EN The serial enable input must remain High during FPGA configuration operations. ...

... FPGA mode pins. In Master mode, the FPGA automatically loads the config- uration program from an external memory. The AT17FxxxA Serial Configuration PROM has been designed for compatibility with the Master Serial mode. This document discusses the Atmel AT40K, AT40KAL and AT94KAL applications as well as Altera applications. 7. Control of Configuration Most connections between the FPGA device and the AT17FxxxA Serial Configurator PROM are simple and self-explanatory ...

... Exposure to Abso- lute Maximum Rating conditions for extended periods of time may affect device reliability. AT17FxxxA Series Configurator Min Max 2.97 3.63 2.97 3.63 AT17F040A AT17F080A Min Max Min 2 0.8 0 2.4 2.4 ...

AC Characteristics nCS RESET/OE CLK T CE DATA 15. AC Characteristics when Cascading RESET/OE nCS CLK T DATA T nCASC 2823D–CNFG–2/08 T SCE CAC CDF LAST BIT T OCK OCE AT17F040A/080A T ...

AC Characteristics Symbol Description ( Data Delay OE (2) T nCS to Data Delay CE (2) T DCLK to Data Delay CAC T Data Hold from nCS, OE, or DCLK OH (3) T nCS or OE ...

... Thin Plastic Quad Flat Package (TQFP) Note: 1. Airflow = 0 ft/min. 2823D–CNFG–2/08 AT17F040A Min Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial θ [° C/W] JC θ (1) [° C/W] JA θ [° C/W] JC θ (1) [° C/W] JA AT17F040A/080A AT17F080A Max Min Max AT17F040A AT17F080A – – Units ...

... Green Package Options (Pb/Halide-free/RoHS Compliant) Memory Size AT17F040A-30CU 4-Mbit AT17F040A-30JU AT17F080A-30CU 8-Mbit AT17F080A-30JU 8CN4 8-lead 1.04 mm, Leadless Array Package (LAP) – Pin-compatible with 8-lead SOIC/VOIC Packages 20J 20-lead, Plastic J-leaded Chip Carrier (PLCC) 32A 32-lead, Thin (1.0 mm) Plastic Quad Flat Package Carrier (TQFP) ...

... TYP Bottom View Note: 1. Metal Pad Dimensions. 2. All exposed metal area shall have the following finished platings. Ni: 0.0005 to 0.015 mm Au: 0.0005 to 0.001 mm Package Drawing Contact: packagedrawings@atmel.com 2823D–CNFG–2/08 D Pin1 Corner TITLE 8CN4, 8-lead ( 1.04 mm Body), Lead Pitch 1.27mm, Leadless Array Package (LAP) ...

PLCC 1.14(0.045) X 45˚ B 0.51(0.020)MAX 45˚ MAX (3X) Notes: 1. This package conforms to JEDEC reference MS-018, Variation AA. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is .010"(0.254 mm) per side. ...

TQFP PIN 0˚~7˚ L Notes: 1. This package conforms to JEDEC reference MS-026, Variation ABA. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 ...

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