VIPER27HDTR STMicroelectronics, VIPER27HDTR Datasheet - Page 21

• Manufacturer Part Number: VIPER27HDTR
• Description: IC OFFLINE CONV PWM OVP OCP 16SO
• Manufacturer: STMicroelectronics
• Series: VIPer™ plusr

Specifications of VIPER27HDTR

• Output Isolation: Isolated
• Frequency Range: 103 ~ 127kHz
• Voltage - Input: 8.5 ~ 23.5 V
• Voltage - Output: 800V
• Power (watts): 24W
• Operating Temperature: -40°C ~ 150°C
• Package / Case: 16-SOIC (0.154", 3.90mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-10068-2

VIPER27
When the feedback pin voltage reaches the threshold V
starts to charge the feedback capacitor (C
V
value of I
During the first start up phase of the converter, after the soft-start up time, t
voltage could force the feedback pin voltage to rise up to the
off the converter itself.
To avoid this event, the appropriate feedback network has to be selected according to the
output load. More the network feedback fixes the compensation loop stability. The
on page 22
The time from the over load detection (V
(V
formula:
Equation 5
In the
as well as it needs to activate the over load protection (see equation 5).
After the start up time, t
capacitor could not be at its nominal value and the controller interprets this situation as an
over load condition. In this case, the OLP delay helps to avoid an incorrect device shut down
during the start up phase.
Owing to the above considerations, the OLP delay time must be long enough to by-pass the
initial output voltage transient and check the over load condition only when the output
voltage is in steady state. The output transient time depends from the value of the output
capacitor and from the load.
When the value of the C
ensure enough OLP delay, an alternative compensation network can be used and it is
showed in
Using this alternative compensation network, two poles (f
introduced by the capacitors C
The capacitor C
is usually used to compensate the high frequency zero due to the ESR (equivalent series
resistor) of the output capacitance of the fly-back converter.
The mathematical expressions of these poles and zero frequency, considering the scheme
in
Equation 6
FBolp
FB
Figure 29
=
threshold, the converter is turned off and the start up phase is activated with reduced
Figure 28
V
FBolp
DDch
Figure 29 on page 22
and
are reported by the equations below:
) can be set by C
to 0.6 mA, see
, the capacitor connected to FB pin (C
FB
Figure 29
introduces a pole (f
SS
FB
, during which the feedback voltage is fixed at
show the two different feedback networks.
capacitor calculated for the loop stability is too low and cannot
T
Table 7 on page 6
FB
Doc ID 15133 Rev 5
OLP delay
FB
.
value (see
and C
–
f
ZFB
PFB
=
FB1
FB
=
2
) at higher frequency than f
FB
C
⋅
=
and the resistor R
Figure 28 on page 22
⋅ π
) and when the feedback voltage reaches the
FB
V
C
FBlin
×
.
FB
1
V
--------------------------------------- -
1
FBolp
) to the device shutdown
⋅
R
FB
3μA
FB
1
–
FBlin
) is part of the compensation circuit
V
PFB
FBlin
an internal current generator
, f
V
FB1
PFB1
FBolp
.
and
) and one zero (f
Operation descriptions
threshold that switches
ZB
Figure 29
and f
V
FBlin
SS
PFB1
, the output
, the output
), using the
. This pole
Figure 28
ZFB
) are
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