VIPER53DIP-E STMicroelectronics, VIPER53DIP-E Datasheet - Page 26

• Manufacturer Part Number: VIPER53DIP-E
• Description: IC OFFLINE SWIT PWM CM OTP 8DIP
• Manufacturer: STMicroelectronics
• Series: VIPER™r
• Type: Pulse Width Modulator Controllerr

Specifications of VIPER53DIP-E

• Output Isolation: Isolated
• Frequency Range: 93 ~ 300kHz
• Voltage - Input: 8.4 ~ 19 V
• Voltage - Output: 620V
• Power (watts): 30W
• Operating Temperature: 25°C ~ 125°C
• Package / Case: 8-DIP (0.300", 7.62mm)
• Current, Supply: 9 mA
• Frequency, Oscillator: 100 kHz
• Package Type: DIP-8
• Regulator Type: Switching
• Resistance, Thermal, Junction To Case: 20 °C/W
• Temperature, Operating, Range: -40 to +150 °C
• Time, Fall: 100 ns
• Time, Rise: 50 ns
• Voltage, Supply: 13 V
• Power Switch Family: VIPer53DIP
• Input Voltage: 0 to 19V
• Power Switch On Resistance: 900mOhm
• Output Current: 1.6A
• Number Of Outputs: Single
• Mounting: Through Hole
• Supply Current: 9mA
• Operating Temperature (min): -40C
• Operating Temperature (max): 150C
• Operating Temperature Classification: Automotive
• Pin Count: 8
• Mounting Style: Through Hole
• For Use With: 497-8435 - BOARD EVAL FOR VIPER53 28W497-6458 - BOARD EVAL BASED ON VIPER53-E497-6262 - BOARD REF SGL VIPER53 90-264VAC497-5866 - EVAL BOARD 24W NEG OUT VIPER53E
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-6171-5

Transconductance error amplifier
26/36
optocoupler, the internal error amplifier is fully used for regulation). A typical schematic
corresponding to this situation can be seen on
The transfer function of the power cell is represented as G(s) in
which depends on the output load and on the output capacitor value. As the load of a
converter may change, two curves are shown for two different values of output resistance
value, R
capacitor ESR. Note: The overall transfer function does not depend on the input voltage
because of the current mode control.
The error amplifier has a fixed behavior, similar to the one shown in
is to avoid injection of high frequency noise in the current mode section. A zero due to the
R
The total transfer function is shown as F(s). G(s) at the bottom of
load (plain line), the load pole is exactly compensated by the zero of the error amplifier, and
the result is a perfect first order decreasing until it reaches the zero of the output capacitor
ESR. The error amplifier cut-off then definitely any further spurious noise or resonance from
disturbing the regulation loop.
The point where the complete transfer function has a unity gain is known as the regulation
bandwidth and has:
In
The dynamic load regulation is improved by increasing the regulation bandwidth, but some
limitations have to be respected: As the transfer function above the zero due the capacitor
ESR is not reliable (The ESR itself is not well specified, and other parasitic effects may take
place), the bandwidth should always be lower than the minimum of F
As the highest bandwidth is obtained with the highest output power (Plain line with R
in
value of R
range. The following formula can be derived:
Equation 12
With:
COMP
Figure
Figure
–
–
-C
P
L1
OUT2
COMP
24, the unity gain is reached in a first order slope, so the stability is ensured.
The higher it is, the faster the reaction will be to an eventual load change, and the
smaller the output voltage change will be.
The phase shift in the complete system at this point has to be less than 135° to
ensure good stability. Generally, a first-order slope gives 90° of phase shift, and a
second-order gives 180°.
24), the above criteria will be checked for this condition and allows to define the
COMP
and R
=
network is set at the same value as the maximum load R
, as the error amplifier gain depends only on this value for this frequency
V
--------------
L2
R
2
OUT
L2
. A zero at higher frequency values then appears, due to the output
R
COMP
=
P
---------------- -
P
OUT2
MAX
F
----------------------------------------------------- -
BW2
Figure
R
Gm
18.
L2
and:
C
OUT
P
MAX
Figure 24
=
Figure
Figure
C
1
-- -
2
and ESR zero.
L2
L
P
24. For maximum
Iexhibits a pole
23. Its bandwidth
pole.
I
2
LIM
VIPer53 - E
F
SW
L2
load