ICE3A0565 Infineon Technologies, ICE3A0565 Datasheet - Page 14

• Manufacturer Part Number: ICE3A0565
• Description: IC OFFLINE CTRLR SMPS CM 8DIP
• Manufacturer: Infineon Technologies
• Series: CoolSET®F3r

Specifications of ICE3A0565

• Output Isolation: Isolated
• Frequency Range: 92 ~ 108kHz
• Voltage - Input: 8.5 ~ 22 V
• Voltage - Output: 650V
• Power (watts): 25W
• Operating Temperature: -25°C ~ 130°C
• Package / Case: 8-DIP (0.300", 7.62mm)
• Input Voltage: 21V
• Output Voltage: 650V
• Power Dissipation Pd: 25W
• Supply Voltage Range: 8.5V To 21V
• Voltage Regulator Case Style: DIP
• No. Of Pins: 8
• Operating Temperature Range: -40°C To +150°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: ICE3A0565X; ICE3A0565XK; SP000015073

3.5
Figure 12
There is a cycle by cycle Current Limiting realized by the
Current-Limit comparator C10 to provide an overcurrent
detection. The source current of the internal CoolMOS™ is
sensed via an external sense resistor R
R
V
exceeds the internal threshold voltage V
C10 immediately turns off the gate drive by resetting the
PWM Latch FF1. A Propagation Delay Compensation is
added to support the immediate shut down without delay of
the internal CoolMOS™ in case of Current Limiting. The
influence of the AC input voltage on the maximum output
power can thereby be avoided.
To prevent the Current Limiting from distortions caused by
leading edge spikes a Leading Edge Blanking is integrated in
the current sense path for the comparators C10, C12 and the
PWM-OP.
The output of comparator C12 is activated by the Gate G10
if Active Burst Mode is entered. Once activated the current
limiting is thereby reduced to 0.257V. This voltage level
determines the power level when the Active Burst Mode is
left if there is a higher power demand.
Version 2.0
Sense
Sense
PWM Latch
FF1
PWM-OP
the source current is transformed to a sense voltage
which is fed into the pin CS. If the voltage V
Active Burst
Mode
G10
Current Limiting
&
Current Limiting Block
Propagation-Delay
Compensation
CS
C10
C12
10k
0.257V
V
D1
csth
Sense
csth
Current Limiting
Blanking
the comparator
Leading
. By means of
220ns
Edge
1pF
Sense
14
3.5.1
Figure 13
Each time when the internal CoolMOS™ is switched on, a
leading edge spike is generated due to the primary-side
capacitances and secondary-side rectifier reverse recovery
time. This spike can cause the gate drive to switch off
unintentionally. To avoid a premature termination of the
switching pulse, this spike is blanked out with a time
constant of t
not be switched off.
3.5.2
In case of overcurrent detection, the switch-off of the
internal CoolMOS™ is delayed due to the propagation delay
of the circuit. This delay causes an overshoot of the peak
current I
current (see Figure 14).
Figure 14
The overshoot of Signal2 is bigger than of Signal1 due to the
steeper rising waveform. This change in the slope is
depending on the AC input voltage. Propagation Delay
Compensation is integrated to limit the overshoot
dependency on dI/dt of the rising primary current. That
means the propagation delay time between exceeding the
current sense threshold V
CoolMOS™ is compensated over temperature within a wide
range.
I
I
I
peak2
peak1
Limit
V
csth
I
V
Sense
Sense
peak
LEB
Propagation Delay Compensation
which depends on the ratio of dI/dt of the peak
Leading Edge Blanking
Leading Edge Blanking
Current Limiting
I
= 220ns. During this time, the gate drive will
Overshoot2
Signal1
csth
and the switch off of the internal
t
Functional Description
LEB
= 220ns
CoolSET™-F3
Signal2
t
Propagation Delay
24 Aug 2005
I
Overshoot1
t
t