IC SWIT PWM SMPS CM PENTAWATT5

VIPER100A(022Y)

Manufacturer Part NumberVIPER100A(022Y)
DescriptionIC SWIT PWM SMPS CM PENTAWATT5
ManufacturerSTMicroelectronics
SeriesVIPER™
VIPER100A(022Y) datasheets
 


Specifications of VIPER100A(022Y)

Output IsolationIsolatedFrequency Range90 ~ 200kHz
Voltage - Input8 ~ 15 VVoltage - Output700V
Power (watts)82WOperating Temperature25°C ~ 125°C
Package / CasePentawatt-5 HV (Bent and Staggered Leads)Number Of Outputs1
Output Voltage700 VOutput Current3000 mA
Mounting StyleThrough HoleSwitching Frequency90 KHz to 110 KHz
Operating Supply Voltage0 V to 15 VFall Time100 ns
Rise Time50 nsSynchronous PinNo
Lead Free Status / RoHS StatusContains lead / RoHS non-compliantOther names497-2656-5
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Transconductance Error Amplifier
The VIPer100/100A includes a transconductance error amplifier. Transconductance Gm is the change in
output current (I
) versus change in input voltage (V
COMP
The output impedance Z
COMP
This last equation shows that the open loop gain A
A
= G
x Z
VOL
m
COMP
where G
value for VIPer100/100A is 1.5 mA/V typically.
m
G
is defined by specification, but Z
m
impedance Z can be connected between the COMP pin and ground in order to define the transfer
function F of the error amplifier more accurately, according to the following equation (very similar to the
one above):
F
= Gm x Z(S)
(S)
The error amplifier frequency response is reported in figure 10 page 8 for different values of a simple
resistance connected on the COMP pin. The unloaded transconductance error amplifier shows an
internal Z
of about 330KΩ. More complex impedance can be connected on the COMP pin to achieve
COMP
different compensation level. A capacitor will provide an integrator function, thus eliminating the DC static
error, and a resistance in series leads to a flat gain at higher frequency, insuring a correct phase margin.
This configuration is illustrated in (see Figure 21) page 17.
As shown in (see Figure 21) an additional noise filtering capacitor of 2.2nF is generally needed to avoid
any high frequency interference.
Is also possible to implement a slope compensation when working in continuous mode with duty cycle
higher than 50%. (see Figure 22) shows such a configuration. Note: R1 and C2 build the classical
compensation network, and Q1 is injecting the slope compensation with the correct polarity from the
oscillator sawtooth.
External Clock Synchronization:
The OSC pin provides a synchronisation capability when connected to an external frequency source.
(see Figure 23) page17 shows one possible schematic to be adapted, depending the specific needs. If
the proposed schematic is used, the pulse duration must be kept at a low value (500ns is sufficient) for
minimizing consumption. The optocoupler must be able to provide 20mA through the optotransistor.
Primary Peak Current Limitation
The primary I
current and, consequently, the output power can be limited using the simple circuit
DPEAK
shown in (see Figure 24) page 18. The circuit based on Q1, R
pin in order to limit the primary peak current of the device to a value:
where:
R 1
+
R 2
×
- --- -- - --- -- - -- - -- - -
V COM P
=
0.6
R
2
The suggested value for R
+R
1
16/24
). Thus:
DD
∂ I C OM P
G
=
-- - -- - -- - --- -- - -- - -- - -- -
∂ V DD
m
at the output of this amplifier (COMP pin) can be defined as:
∂ V COMP
∂ V COMP
1
-- - -- --- - -- - -- --- - -- - --- - -
-- - --- -- -
×
- -- --- - -- - -- --- - -- - --- -- - -
Z
=
=
∂ I CO MP
∂ V DD
CO MP
G
m
can be related to G
VOL
and therefore A
COMP
is in the range of 220KΩ.
2
VIPer100/SP - VIPer100A/ASP
and Z
:
m
COMP
are subject to large tolerances. An
VOL
and R
clamps the voltage on the COMP
1
2
V C OM P
0.5
I
=
- -- - -- - -- - --- -- --- - -- - --- -- --- - -- - - -
D PEAK
H ID