LTC4006EGN-2 Linear Technology, LTC4006EGN-2 Datasheet - Page 17

• Manufacturer Part Number: LTC4006EGN-2
• Description: IC CHARGER BATTERY 4A 16-SSOP
• Manufacturer: Linear Technology

Specifications of LTC4006EGN-2

• Function: Charge Management
• Battery Type: Lithium-Ion (Li-Ion)
• Voltage - Supply: 6 V ~ 28 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-SSOP (0.150", 3.90mm Width)
• Output Current: 4A
• Output Voltage: 12.6V
• Operating Supply Voltage (min): 6V
• Operating Supply Voltage (max): 28V
• Operating Temp Range: -40C to 85C
• Package Type: SSOP N
• Mounting: Surface Mount
• Pin Count: 16
• Operating Temperature Classification: Industrial
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

APPLICATIO S I FOR ATIO
0V keeping Q1B in the off state while P-channel MOSFET
Q1A is on. If V
diode will provide a passive but instant discharge path for
battery current to reach V
internal diode has the same current rating as the FET itself,
but has a very high V
quickly build up in Q1B if left alone. However as V
falls below V
on shorting out its internal diode removing both the heat
and voltage losses created by the diode. When V
zero volts, Q1B gate will be driven to the same voltage as
V
diode along with a 100k resistor in series with the Q1B gate
protects the gate from any hazardous voltage spikes that
can exceed Q1B maximum permissible V
zener voltage rating must be less than Q1B V
age but greater than V
Since Q1A and Q1B are always at opposite states and share
the same load, it is often advantagous to combine both FETs
into a single package and save PCB space. The P
the FET that is on is enhanced when the other FET is off. The
choice of a combined Q1 should take into account the high-
est load current conditions of both paths and choose
whichever is greater as the driving force behind the MOSFET
BAT
V
providing the lowest possible RDS
IN
Q1A
BAT
Figure 12. Optional Simple High
Efficiency Battery Discharge Path
IN
by Q1B’s V
were to suddenly go away, Q1B internal
TGATE
U
f
100k
BAT
of about a volt such that heat will
INDUCTOR
.
U
OUT
GS
threshold, Q1B will then turn
and hold up the load. Q1B
ZENER
R
W
SENSE
18V
ON
4006 F12
GS
value. A zener
GS(MAX)
voltage. The
IN
U
Q1B
’s voltage
IN
D
V
V
falls to
rate of
OUT
BAT
volt-
selection. If the V
such that Q1B is not turned on quickly enough for the given
load and stay within its P
able Schottky diode in parallel with Q1B.
PCB Layout Considerations
For maximum efficiency, the switch node rise and fall times
should be minimized. To prevent magnetic and electrical
field radiation and high frequency resonant problems,
proper layout of the components connected to the IC is
essential. (See Figure 13.) Here is a PCB layout priority list
for proper layout. Layout the PCB using this specific order.
1. Input capacitors need to be placed as close as possible
2. The control IC needs to be close to the switching FET’s
3. Place inductor input as close as possible to switching
to switching FET’s supply and ground connections.
Shortest copper trace connections possible. These
parts must be on the same layer of copper. Vias must
not be used to make this connection.
gate terminals. Keep the gate drive signals short for a
clean FET drive. This includes IC supply pins that con-
nect to the switching FET source pins. The IC can be
placed on the opposite side of the PCB relative to above.
FET’s output connection. Minimize the surface area of
this trace. Make the trace width the minimum amount
needed to support current—no copper fills or pours.
Avoid running the connection using multiple layers in
parallel. Minimize capacitance from this node to any
other trace or plane.
V
IN
Figure 13. High Speed Switching Path
C2
IN
CIRCULATING
FREQUENCY
supply is going to collapse very slowly
SWITCH NODE
PATH
HIGH
D
limits, you should install a suit-
L1
D1
LTC4006
C3
17
4006 F13
BAT
V
4006fa
BAT