ISL88731CHRTZ Intersil, ISL88731CHRTZ Datasheet - Page 18

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ISL88731CHRTZ

Manufacturer Part Number
ISL88731CHRTZ
Description
IC BATT CHRGR SMBUS LVL2 28TQFN
Manufacturer
Intersil
Datasheet

Specifications of ISL88731CHRTZ

Function
Charge Management
Battery Type
Lithium-Ion (Li-Ion)
Voltage - Supply
8 V ~ 26 V
Operating Temperature
-10°C ~ 100°C
Mounting Type
Surface Mount
Package / Case
28-WFQFN Exposed Pad
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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output voltage. The RMS value of the output ripple current I
is given by Equation 6:
Where the duty cycle D is the ratio of the output voltage (battery
voltage) over the input voltage for continuous conduction mode
which is typical operation for the battery charger. During the
battery charge period, the output voltage varies from its initial
battery voltage to the rated battery voltage. So, the duty cycle
varies from 0.53 for the minimum battery voltage of 7.5V
(2.5V/Cell) to 0.88 for the maximum battery voltage of 12.6V.
The maximum RMS value of the output ripple current occurs at
the duty cycle of 0.5 and is expressed as Equation 7:
For V
maximum RMS current is 0.19A. A typical 20µF ceramic
capacitor is a good choice to absorb this current and also has
very small size. Organic polymer capacitors have high
capacitance with small size and have a significant equivalent
series resistance (ESR). Although ESR adds to ripple voltage, it
also creates a high frequency zero that helps the closed loop
operation of the buck regulator.
EMI considerations usually make it desirable to minimize ripple
current in the battery leads. Beads may be added in series with
the battery pack to increase the battery impedance at 400kHz
switching frequency. Switching ripple current splits between the
battery and the output capacitor depending on the ESR of the
output capacitor and battery impedance. If the ESR of the output
capacitor is 10mΩ and battery impedance is raised to 2Ω with a
bead, then only 0.5% of the ripple current will flow in the battery.
MOSFET Selection
The Notebook battery charger synchronous buck converter has
the input voltage from the AC-adapter output. The maximum
AC-adapter output voltage does not exceed 25V. Therefore, 30V
logic MOSFET should be used.
The high-side MOSFET must be able to dissipate the conduction
losses plus the switching losses. For the battery charger
application, the input voltage of the synchronous buck converter
is equal to the AC-adapter output voltage, which is relatively
constant. The maximum efficiency is achieved by selecting a
high side MOSFET that has the conduction losses equal to the
switching losses. Switching losses in the low-side FET are very
small. The choice of low-side FET is a trade-off between
conduction losses (r
the r
FET.
The LGATE gate driver can drive sufficient gate current to switch
most MOSFETs efficiently. However, some FETs may exhibit cross
conduction (or shoot-through) due to current injected into the
drain-to-source parasitic capacitor (C
edge at the phase node when the high side MOSFET turns on.
Although LGATE sink current (1.8A typical) is more than enough
to switch the FET off quickly, voltage drops across parasitic
I Cout
I Cout
(
(
DS(ON)
IN,MAX
)
)
RMS
RMS
of the low-side FET is 2x the r
= 19V, VBAT = 16.8V, L = 10µH, and f
=
=
----------------------------------------- -
4
--------------------------------- - D
12 L F
V
V
IN MAX
12 L F
IN MAX
⋅ ⋅
DS(ON)
,
,
⋅ ⋅
SW
SW
) and cost. A good rule of thumb for
18
(
1 D
gd
)
) by the high dV/dt rising
DS(ON)
of the high-side
s
= 400kHz, the
ISL88731C
(EQ. 6)
(EQ. 7)
RMS
impedances between LGATE and the MOSFET can allow the gate
to rise during the fast rising edge of voltage on the drain.
MOSFETs with low threshold voltage (<1.5V) and low ratio of
C
for a few ns by the high dV/dt (rising edge) on their drain. This
can be avoided with higher threshold voltage and C
Another way to avoid cross conduction is slowing the turn-on
speed of the high-side MOSFET by connecting a resistor between
the BOOT pin and the bootstrap capacitor.
For the high-side MOSFET, the worst-case conduction losses
occur at the minimum input voltage, as shown in Equation 8:
The optimum efficiency occurs when the switching losses equal
the conduction losses. However, it is difficult to calculate the
switching losses in the high-side MOSFET since it must allow for
difficult-to-quantify factors that influence the turn-on and turn-off
times. These factors include the MOSFET internal gate
resistance, gate charge, threshold voltage, stray inductance and
the pull-up and pull-down resistance of the gate driver.
The following switching loss calculation (Equation 9) provides a
rough estimate.
where the following are the peak gate-drive source/sink current
of Q
• Q
• Q
• I
• I
• I
• I
Low switching loss requires low drain-to-gate charge Q
Generally, the lower the drain-to-gate charge, the higher the
ON-resistance. Therefore, there is a trade-off between the
ON-resistance and drain-to-gate charge. Good MOSFET selection
is based on the Figure of Merit (FOM), which is a product of the
total gate charge and on-resistance. Usually, the smaller the
value of FOM, the higher the efficiency for the same application.
For the low-side MOSFET, the worst-case power dissipation
occurs at minimum battery voltage and maximum input voltage
as shown in Equation 10.
Choose a low-side MOSFET that has the lowest possible
ON-resistance with a moderate-sized package (like the 8 Ld
SOIC) and is reasonably priced. The switching losses are not an
issue for the low-side MOSFET because it operates at
zero-voltage-switching.
P
1
-- - V
2
P
P
gs
Q1 Switching
Q2
Q1 conduction
MOSFET,
IN
LV
LP
g,sink
g
/C
gd
rr
,
1
,
,
source
I
: inductor valley current,
=
: total reverse recovery charge of the body-diode in low-side
: Inductor peak current,
, respectively:
LV
gd
: drain-to-gate charge,
f
1
sw
(<5) and high gate resistance (>4Ω) may be turned on
V
------------ -
----------------------- -
I
V
g source
OUT
,
IN
Q
=
gd
=
V
------------ - I
I
V
BAT
OUT
IN
+
2
1
-- - V
2
BAT
r
IN
DS ON
I
2
LP
(
f
r
sw
DS ON
)
(
---------------- -
I
g
Q
,
gd
sin
)
k
+
Q
rr
V
IN
f
gs
sw
February 8, 2011
/C
gd
gd
.
FN6978.2
(EQ. 10)
(EQ. 8)
ratio.
(EQ. 9)

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