ISL88731CHRTZ Intersil, ISL88731CHRTZ Datasheet - Page 22

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ISL88731CHRTZ

Manufacturer Part Number
ISL88731CHRTZ
Description
IC BATT CHRGR SMBUS LVL2 28TQFN
Manufacturer
Intersil
Datasheet

Specifications of ISL88731CHRTZ

Function
Charge Management
Battery Type
Lithium-Ion (Li-Ion)
Voltage - Supply
8 V ~ 26 V
Operating Temperature
-10°C ~ 100°C
Mounting Type
Surface Mount
Package / Case
28-WFQFN Exposed Pad
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Compensation Break Frequency Equations
F
F
F
F
F
Choose R
Equation 29.
R
Next, choose C
from Equation 30.
C
PCB Layout Considerations
Power and Signal Layers Placement on the
PCB
As a general rule, power layers should be close together, either
on the top or bottom of the board, with signal layers on the
opposite side of the board. As an example, layer arrangement on
a 4-layer board is shown in the following:
F
ZERO1
ZERO2
LC
POLE1
ESR
FILTER
VCOMP
VCOMP
FIGURE 28. ASYMPTOTIC BODE PLOT OF THE VOLTAGE
=
-20
-40
-60
=
60
40
20
------------------------------
(
0
2π L C
0.1k
=
---------------------------------------- -
(
=
=
=
=
2π C
=
VCOMP
-------------------------------------- -
(
---------------------------------------------------------------- -
(
---------------------------------------- -
(
--------------------------------------------------------------------- -
(
2π RS2 C
(
2π C
1
--------------------------------- -
2π RS2 C
2π R
0.7 F
0.3 F
R
o
1
VCOMP
VCOMP
CONTROL LOOP GAIN
o
COMPENSATOR
MODULATOR
LOOP
)
1
VCOMP
R
equal or lower than the value calculated from
F
F2
1
LC
LC
ZERO1
ESR
)
)
C
1k
1
)
(
F2
o
(
equal or higher than the value calculated
o
1
2π C
2π R
)
)
R
VCOMP
FREQUENCY (Hz)
------------------- -
R
4
o
VCOMP
R
22
+
4
RS2
R
)
F
10k
3
ZERO2
)
)
gm1
------------
----------- -
gm1
5
5
F
LC
F
ESR
100k
R
------------------- -
3
F
R
+
FILTER
4
F
R
POLE1
4
ISL88731C
1M
(EQ. 23)
(EQ. 24)
(EQ. 25)
(EQ. 27)
(EQ. 28)
(EQ. 29)
(EQ. 30)
(EQ. 26)
Separate the power voltage and current flowing path from the
control and logic level signal path. The controller IC will stay on
the signal layer, which is isolated by the signal ground to the
power signal traces.
Component Placement
The power MOSFET should be close to the IC so that the gate drive
signal, the LGATE, UGATE, PHASE, and BOOT, traces can be short.
Place the components in such a way that the area under the IC
has less noise traces with high dv/dt and di/dt, such as gate
signals and phase node signals.
Signal Ground and Power Ground Connection
At minimum, a reasonably large area of copper, which will shield
other noise couplings through the IC, should be used as signal
ground beneath the IC. The best tie-point between the signal
ground and the power ground is at the negative side of the output
capacitor on each side, where there is little noise; a noisy trace
beneath the IC is not recommended.
GND and VCC Pin
At least one high quality ceramic decoupling capacitor should be
used to cross these two pins. The decoupling capacitor can be
put close to the IC.
LGATE Pin
This is the gate drive signal for the bottom MOSFET of the buck
converter. The signal going through this trace has both high dv/dt
and high di/dt, and the peak charging and discharging current is
very high. These two traces should be short, wide, and away from
other traces. There should be no other traces in parallel with
these traces on any layer.
PGND Pin
PGND pin should be laid out to the negative side of the relevant
output capacitor with separate traces.The negative side of the
output capacitor must be close to the source node of the bottom
MOSFET. This trace is the return path of LGATE.
PHASE Pin
This trace should be short, and positioned away from other weak
signal traces. This node has a very high dv/dt with a voltage
swing from the input voltage to ground. No trace should be in
parallel with it. This trace is also the return path for UGATE.
Connect this pin to the high-side MOSFET source.
UGATE Pin
This pin has a square shape waveform with high dv/dt. It
provides the gate drive current to charge and discharge the top
MOSFET with high di/dt. This trace should be wide, short, and
away from other traces, similar to the LGATE.
1. Top Layer: signal lines, or half board for signal lines and the
2. Signal Ground
3. Power Layers: Power Ground
4. Bottom Layer: Power MOSFET, Inductors and other Power
other half board for power lines
traces
February 8, 2011
FN6978.2

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