ISL88731CHRTZ-T Intersil, ISL88731CHRTZ-T Datasheet - Page 17

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ISL88731CHRTZ-T

Manufacturer Part Number
ISL88731CHRTZ-T
Description
IC BATT CHRGR SMBUS LVL2 28TQFN
Manufacturer
Intersil
Datasheet

Specifications of ISL88731CHRTZ-T

Function
Charge Management
Battery Type
Lithium-Ion (Li-Ion)
Voltage - Supply
8 V ~ 26 V
Operating Temperature
-10°C ~ 100°C
Mounting Type
Surface Mount
Package / Case
28-WFQFN Exposed Pad
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Charger Timeout
The ISL88731C includes 2 timers to insure the SMBus master is
active and to prevent overcharging the battery. ISL88731C will
terminate charging if the charger has not received a write to the
ChargeVoltage or ChargeCurrent register within 175s or if the
SCL line is low for more than 25ms. If a time-out occurs, either
ChargeVoltage or ChargeCurrent registers must be written to re-
enable charging.
ISL88731C Data Byte Order
Each register in ISL88731C contains 16-bits or 2, 8 bit bytes. All
data sent on the SMBus is in 8-bit bytes and 2 bytes must be
written or read from each register in ISL88731C. The order in
which these bytes are transmitted appears reversed from the
way they are normally written. The LOW byte is sent first and the
HI byte is sent second. For example, when writing 0x41A0, 0xA0
is written first and 0x41 is sent second.
Writing to the Internal Registers
In order to set the charge current, charge voltage or input current,
valid 16-bit numbers must be written to ISL88731C’s internal
registers via the SMBus.
To write to a register in the ISL88731C, the master sends a
control byte with the R/W bit set to 0, indicating a write. If it
receives an Acknowledge from the ISL88731C it sends a register
address byte setting the register to be written (i.e. 0x14 for the
ChargeCurrent register). The ISL88731C will respond with an
Acknowledge. The master then sends the lower data byte to be
written into the desired register. The ISL88731C will respond with
an Acknowledge. The master then sends the higher data byte to
be written into the desired register. The ISL88731C will respond
with an Acknowledge. The master then issues a Stop condition,
indicating to the ISL88731C that the current transaction is
complete. Once this transaction completes the ISL88731C will
begin operating at the new current or voltage.
ISL88731C does not support writing more than one register per
transaction.
Reading from the Internal
Registers
The ISL88731C has the ability to read from 5 internal registers.
Prior to reading from an internal register, the master must first
select the desired register by writing to it and sending the registers
address byte. This process begins by the master sending a control
byte with the R/W bit set to 0, indicating a write. Once it receives
an Acknowledge from the ISL88731C it sends a register address
byte representing the internal register it wants to read. The
ISL88731C will respond with an Acknowledge. The master must
then respond with a Stop condition. After the Stop condition the
master follows with a new Start condition, then sends a new
control byte with the ISL88731C slave address and the R/W bit set
to 1, indicating a read. The ISL88731C will Acknowledge then send
the lower byte stored in that register. After receiving the byte, the
master Acknowledges by holding SDA low during the 9th clock
pulse. ISL88731C then sends the higher byte stored in the register.
After the second byte neither device holds SDA low (No
17
ISL88731C
Acknowledge). The master will then produce a Stop condition to
end the read transaction.
ISL88731C does not support reading more than 1 register per
transaction.
Application Information
The following battery charger design refers to the “Typical
Application Circuit” (see Figure 4), where typical battery
configuration of 3S2P is used. This section describes how to
select the external components including the inductor, input and
output capacitors, switching MOSFETs and current sensing
resistors.
Inductor Selection
The inductor selection has trade-offs between cost, size,
crossover frequency and efficiency. For example, the lower the
inductance, the smaller the size, but ripple current is higher. This
also results in higher AC losses in the magnetic core and the
windings, which decreases the system efficiency. On the other
hand, the higher inductance results in lower ripple current and
smaller output filter capacitors, but it has higher DCR (DC
resistance of the inductor) loss, lower saturation current and has
slower transient response. So, the practical inductor design is
based on the inductor ripple current being ±15% to ±20% of the
maximum operating DC current at maximum input voltage.
Maximum ripple is at 50% duty cycle or V
required inductance for ±15% ripple current can be calculated
from Equation 3:
Where V
switching frequency and I
inductor.
For V
f
closest standard value gives L = 10µH. Ferrite cores are often the
best choice since they are optimized at 400kHz to 600kHz
operation with low core loss. The core must be large enough not
to saturate at the peak inductor current I
Inductor saturation can lead to cascade failures due to very high
currents. Conservative design limits the peak and RMS current in
the inductor to less than 90% of the rated saturation current.
Crossover frequency is heavily dependent on the inductor value.
F
conservative design has F
frequency. The highest F
battery removed and may be calculated (approximately) from
Equation 5:
Output Capacitor Selection
The output capacitor in parallel with the battery is used to absorb
the high frequency switching ripple current and smooth the
L
I
F
s
PEAK
CO
CO
=
= 400kHz, the calculated inductance is 9.3µH. Choosing the
should be less than 20% of the switching frequency and a
------------------------------------------------------ -
4 F
=
IN,MAX
=
5 11 RS2
------------------------------ -
IN,MAX
SW
I
L MAX
2π L ⋅
V
,
IN MAX
= 20V, V
0.3 I ⋅
,
is the maximum input voltage, F
+
1
-- -
2
L MAX
,
BAT
I
RIPPLE
CO
= 12.6V, I
L,MAX
CO
is in voltage control mode with the
less than 10% of the switching
is the max DC current in the
BAT,MAX
Peak
BAT
= 4.5A, and
= V
in Equation 4:
SW
IN,MAX
is the
February 8, 2011
/2. The
FN6978.2
(EQ. 3)
(EQ. 4)
(EQ. 5)

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