ISL88731HRZ-T Intersil, ISL88731HRZ-T Datasheet - Page 11

IC BATT CHRGR SMBUS LVL2 28-TQFN

ISL88731HRZ-T

Manufacturer Part Number
ISL88731HRZ-T
Description
IC BATT CHRGR SMBUS LVL2 28-TQFN
Manufacturer
Intersil
Datasheet

Specifications of ISL88731HRZ-T

Function
Charge Management
Battery Type
Lithium-Ion (Li-Ion)
Voltage - Supply
8 V ~ 26 V
Operating Temperature
-10°C ~ 100°C
Mounting Type
Surface Mount
Package / Case
28-TQFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
START and STOP Conditions
As shown in Figure 16, START condition is a HIGH-to-LOW
transition of the SDA line while SCL is HIGH.
The STOP condition is a LOW-to-HIGH transition on the SDA
line while SCL is HIGH. A STOP condition must be sent before
each START condition.
Acknowledge
Each address and data transmission uses 9-clock pulses. The
ninth pulse is the acknowledge bit (ACK). After the start
condition, the master sends 7-slave address bits and a R/W bit
during the next 8-clock pulses. During the ninth clock pulse, the
device that recognizes its own address holds the data line low
to acknowledge. The acknowledge bit is also used by both the
master and the slave to acknowledge receipt of register
addresses and data (see Figure 17).
SDA
SCL
CONDITION
START
S
FIGURE 16. START AND STOP WAVEFORMS
S
S
Write To A Register
SLAVE
ADDR + W
Read From A Register
SLAVE
ADDR + W
S
P
START
STOP
11
A
A
REGISTER
REGISTER
FIGURE 18. SMBus/ISL88731 READ AND WRITE PROTOCOL
ADDR
ADDR
A
N
CONDITION
A
A
STOP
ACKNOWLEDGE
NO ACKNOWLEDGE
P
P
LO BYTE
DATA
ISL88731
S
SLAVE
ADDR + R
A
START
SDA
SCL
SMBus Transactions
All transactions start with a control byte sent from the SMBus
master device. The control byte begins with a Start condition,
followed by 7-bits of slave address (0001001 for the ISL88731)
followed by the R/W bit. The R/W bit is 0 for a write or 1 for a
read. If any slave devices on the SMBus bus recognize their
address, they will Acknowledge by pulling the serial data (SDA)
line low for the last clock cycle in the control byte. If no slaves
exist at that address or are not ready to communicate, the data
line will be 1, indicating a Not Acknowledge condition.
Once the control byte is sent, and the ISL88731
acknowledges it, the 2nd byte sent by the master must be a
register address byte such as 0x14 for the ChargeCurrent
register. The register address byte tells the ISL88731 which
register the master will write or read. See Table 1 for details
of the registers. Once the ISL88731 receives a register
address byte it responds with an acknowledge.
HI BYTE
DATA
A
FIGURE 17. ACKNOWLEDGE ON THE I
LO BYTE
MSB
DATA
1
A
DRIVEN BY THE MASTER
DRIVEN BY ISL88731
P
A
2
HI BYTE
DATA
8
N
2
C BUS
ACKNOWLEDGE
FROM SLAVE
P
February 8, 2011
9
FN9258.2

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