TC7116CPL Microchip Technology, TC7116CPL Datasheet - Page 11

IC ADC 3 1/2DGT LCD DVR 40-DIP

TC7116CPL

Manufacturer Part Number
TC7116CPL
Description
IC ADC 3 1/2DGT LCD DVR 40-DIP
Manufacturer
Microchip Technology
Datasheet

Specifications of TC7116CPL

Display Type
LCD
Configuration
7 Segment
Digits Or Characters
A/D 3.5 Digits
Current - Supply
800µA
Voltage - Supply
9V
Operating Temperature
0°C ~ 70°C
Mounting Type
Through Hole
Package / Case
40-DIP (0.600", 15.24mm)
Resolution (bits)
3.5bit
Input Channel Type
Differential
Data Interface
Parallel
Supply Voltage Range - Analogue
9V
Supply Current
800µA
No. Of Pins
40
Operating Temperature Range
0°C To
Digital Ic Case Style
DIP
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Interface
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant

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Company
Part Number
Manufacturer
Quantity
Price
Part Number:
TC7116CPL
Manufacturer:
WR
Quantity:
6 227
Part Number:
TC7116CPL
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
3.2.1
The clocking method used for the TC7116/TC7116A
and TC7117/TC7117A is shown in Figure . Three
clocking methods may be used:
1.
2.
3.
The oscillator frequency is ÷4 before it clocks the
decade counters. It is then further divided to form the
three convert cycle phases: Signal Integrate (1000
counts), Reference De-integrate (0 to 2000 counts),
and Auto-Zero (1000 to 3000 counts). For signals less
than full scale, auto-zero gets the unused portion of ref-
erence de-integrate. This makes a complete measure
cycle of 4000 (16,000 clock pulses), independent of
input voltage. For 3 readings per second, an oscillator
frequency of 48kHz would be used.
FIGURE 3-6:
© 2006 Microchip Technology Inc.
OSC1
An external oscillator connected to Pin 40.
A crystal between Pins 39 and 40.
An RC network using all three pins.
40
Typical Segment Output
Internal Digital Ground
SYSTEM TIMING
V+
Digital Ground
0.5mA
8mA
OSC2
TC7117A
Clock
TC7117
From Comparator Output
TC7117/TC7117A Digital Section
39
Segment
To Switch Drivers
To
V+
OSC3
38
Thousands
÷
4
7-Segment
Hundreds
Decode
Control Logic
To achieve maximum rejection of 60Hz pickup, the sig-
nal integrate cycle should be a multiple of 60Hz. Oscil-
lator frequencies of 240kHz, 120kHz, 80kHz, 60kHz,
48kHz, 40kHz, etc. should be selected. For 50Hz rejec-
tion, oscillator frequencies of 200kHz, 100kHz,
66-2/3kHz, 50kHz, 40kHz, etc. would be suitable. Note
that 40kHz (2.5 readings per second) will reject both
50Hz and 60Hz.
3.2.2
When HLDR is at a logic HIGH, the latch will not be
updated. Analog-to-Digital conversions will continue,
but will not be updated until HLDR is returned to LOW.
To continuously update the display, connect to TEST
(TC7116/TC7116A) or GROUND (TC7117/TC7117A),
or disconnect. This input is CMOS compatible with
70kΩ typical resistance to TEST (TC7116/TC7116A) or
GROUND (TC7117/TC7117A).
HLDR
TC7116/A/TC7117/A
1
7-Segment
Latch
Decode
~70kΩ
Tens
HOLD READING INPUT
7-Segment
Decode
Units
500Ω
DS21457C-page 11
35
37
21
Digital
GND
V+
TEST

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