MM145453V National Semiconductor, MM145453V Datasheet - Page 3

• Manufacturer Part Number: MM145453V
• Description: IC DVR LCD 33 SEG DISPLAY 44PLCC
• Manufacturer: National Semiconductor

Specifications of MM145453V

• Display Type: LCD
• Configuration: 7 Segment + DP, Alphanumeric & Bar Graph
• Digits Or Characters: 4.5 Digits
• Voltage - Supply: 3 V ~ 10 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 44-LCC (J-Lead)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Current - Supply: -
• Interface: -
• Other names: *MM145453V

Timing Diagram
Block Diagram
Applications Information
The MM145453 is specifically designed to operate 4
7-segment displays with minimal interface with the display
and data source. Serial data transfer from the data source to
the display driver is accomplished with 2 signals, serial Data
and Clock. Using a format of a leading "1" followed by the 33
data bits and 2 trailing don’t care bits, allows data transfer
without the need of an additional Data Load signal. Since the
MM145453 does not contain a character generator, the for-
matting of the segment information must be done prior to
inputting the data to the MM145453. The transfer of the 33
data bits is complete at the falling edge of the 36th clock
cycle, thus providing non-multiplexed, direct drive to the
display. Outputs change only if the serial data bits differ from
the previous time.
Figure 3 shows the data input format. A single start bit of
logical ’1’ precedes the 33 bits of segment data for a total of
34 bits that need to be defined and clocked in. After the 34
bits are clocked in, 2 additional clock cycles are required. At
the 36th clock cycle an internal LOAD signal is generated
synchronously with the rising edge of the Clock In signal,
which loads the 33 bits of segment data in the shift register
into the latches. At the falling edge of the 36th clock cycle an
1
⁄
2
digit
FIGURE 1.
FIGURE 2.
3
internal RESET signal is generated which clears all the shift
registers for the next set of data. The shift registers are static
master-slave configuration. There is no clear for the master
portion of the first shift register, thus allowing continuous
operation. The data during the 35th and 36th clock cycles is
"don’t care", but setting data to logical ’0’ for these two clock
cycles is the preferred format.
The data input bits map directly to the segment output pins
and the display. The MM145453 does not have any format
restrictions, as all outputs are controllable.
The MM145453 has an internal oscillator which can gener-
ate the required clock signal to drive the LCD back plane.
The frequency of the internal oscillator is set by a pull-up
resistor (R
and a capacitor (C
to Ground. Due to the current sink limitations of the OSC_IN
circuitry, the lowest recommended resistor value for setting
the oscillator frequency is 9kΩ. It will typically take 2 to 4 RC
time constants to charge the OSC_IN pin from near 0V to
within 1V of V
the OSC_IN circuitry. An approximate calculation of f
f
OSC
= 1 / (lη(V
OSC_IN
DD
DD
which is the high threshold voltage point for
) connected from the OSC_IN pin to V
/1V) X R
OSC_IN
) connected from the OSC_IN pin
OSC_IN
10128302
X C
10128303
OSC_IN
)
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OSC
DD
is:
,