MAX1492CAI+T Maxim Integrated Products, MAX1492CAI+T Datasheet - Page 22

• Manufacturer Part Number: MAX1492CAI+T
• Description: IC ADC W/LCD DRIVER 28-SSOP
• Manufacturer: Maxim Integrated Products

Specifications of MAX1492CAI+T

• Display Type: LCD
• Configuration: 7 Segment + 2 Annunciators
• Interface: Serial
• Digits Or Characters: A/D 3.5 Digits
• Current - Supply: 960µA
• Voltage - Supply: 2.7 V ~ 5.25 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 28-SSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

This register contains the status of the conversion
results.
SIGN:
OVER:
This register is the primary control register for the
MAX1492/MAX1494. It is a 16-bit read/write register. It
is used to indicate the desired clock and reference
3.5- and 4.5-Digit, Single-Chip ADCs
with LCD Drivers
START:
(R/W):
Command Byte (Write Only):
Status Register (Read Only):
Default values: 00h
Control Register (Read/Write):
Default values: 0000h
22
MSB
MSB
MSB
START (1)
SPI/ADC
HOLD
Bit 15
______________________________________________________________________________________
SIGN
Bit 7
Bit 7
Latched Negative-Polarity Indicator.
Latches high when the result is negative.
Clears by reading the status register,
unless the condition remains true.
Overrange Bit. Latches high if an over-
range condition occurs (the ADC result is
larger than the value in the overrange reg-
ister). Clears by reading the status regis-
ter, unless the condition remains true.
Start Bit. The first 1 clocked into the
MAX1492/MAX1494 is the first bit of the
command byte.
Read/Write. Set this bit to 1 to read from
the specified register. Set this bit to 0 to
write to the selected register. Note that
EXTCLK
OVER
Bit 14
PEAK
Bit 6
Bit 6
R/W
RANGE
UNDER
INTREF
Bit 13
Bit 5
Bit 5
RS4
LOW_BATT
DP_EN
Bit 12
Bit 4
CLR
Bit 4
RS3
(RS4–RS0): Register Address Bits. RS4 to RS0 specify
X:
UNDER:
LOW_BATT: Low-Battery Bit. Latches high if the voltage
DRDY:
source. It sets the LCD controls, range modes, power-
down modes, offset calibration, and the reset register
function (CLR).
SEG_SEL
DPSET2
DRDY
Bit 11
Bit 3
Bit 3
RS2
OFFSET_CAL1
certain registers are read-only. Write com-
mands to a read-only register are
ignored.
which register is accessed.
Don’t care.
Underrange Bit. Latches high if an under-
range condition occurs (the ADC result is
less than the value in the underrange regis-
ter). Clears by reading the status register,
unless the condition remains true.
at the LOWBATT is lower than 2.048V (typ).
Clears by reading the status register,
unless the condition remains true.
Data-Ready Bit. Latches high to indicate
a completed conversion result with valid
data. Read the ADC Result-Register 1 to
clear this bit.
DPSET1
Bit 2
Bit 10
RS1
Bit 2
0
OFFSET_CAL2
PD_DIG
Bit 1
RS0
0
Bit 9
Bit 1
PD_ANA
Bit 0
X
0
Bit 8
LSB
Bit 0
0
LSB
LSB