PCF8578H/1,118 NXP Semiconductors, PCF8578H/1,118 Datasheet
PCF8578H/1,118
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PCF8578H/1,118 Summary of contents
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PCF8578 LCD row/column driver for dot matrix graphic displays Rev. 06 — 5 May 2009 1. General description The PCF8578 is a low power CMOS matrix graphic displays at multiplex rates of 1:8, 1:16, 1:24 or 1:32. The device has ...
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... NXP Semiconductors 3. Applications I Automotive information systems I Telecommunication systems I Point-of-sale terminals I Industrial computer terminals I Instrumentation 4. Ordering information Table 1. Type number PCF8578T/1 PCF8578H/1 PCF8578HT/1 [1] Should not be used for new designs. 5. Marking Table 2. Type number PCF8578T/1 PCF8578H/1 PCF8578HT/1 PCF8578_6 Product data sheet LCD row/column driver for dot matrix graphic displays ...
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... NXP Semiconductors 6. Block diagram LCD TEST POWER-ON RESET SCL INPUT FILTERS SDA n.c. n.c. (1) Operates at LCD voltage levels, all other blocks operate at logic levels. Fig 1. Block diagram PCF8578_6 Product data sheet LCD row/column driver for dot matrix graphic displays C39 - C32 ...
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... NXP Semiconductors 7. Pinning information 7.1 Pinning Fig 2. PCF8578_6 Product data sheet LCD row/column driver for dot matrix graphic displays 1 SDA SCL 2 SYNC 3 4 CLK TEST 6 SA0 7 8 OSC LCD 15 n.c. n.c. 16 C39 17 18 C38 19 C37 C36 20 C35 21 22 C34 C33 23 C32 ...
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... NXP Semiconductors Fig 3. PCF8578_6 Product data sheet LCD row/column driver for dot matrix graphic displays SDA 7 8 SCL PCF8578H SYNC 9 CLK TEST SA0 13 n. n.c. 16 OSC Top view. For mechanical details, see Figure Pinning diagram of PCF8578H/1 (LQFP64) Rev. 06 — 5 May 2009 ...
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... NXP Semiconductors Fig 4. PCF8578_6 Product data sheet LCD row/column driver for dot matrix graphic displays SDA 7 8 SCL PCF8576HT SYNC 9 CLK TEST SA0 13 n. n.c. 16 OSC Top view. For mechanical details, see Figure Pinning diagram of PCF8578HT/1 (TQFP64) Rev. 06 — 5 May 2009 ...
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... NXP Semiconductors 7.2 Pin description Table 3. Symbol SDA SCL SYNC CLK V SS [1] TEST SA0 OSC LCD n.c. C39 to C32 R31/C31 to R8/ [1] The TEST pin must be connected to V PCF8578_6 Product data sheet LCD row/column driver for dot matrix graphic displays Pin description ...
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... NXP Semiconductors 8. Functional description 8.1 Display configurations The PCF8578 row and column driver is designed for use in one of three ways: • Stand-alone row and column driver for small displays (mixed mode) • Row and column driver with cascaded PCF8579s (mixed mode) • ...
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HOST C MICROCONTROLLER SCL C SDA Fig 5. Typical mixed mode configuration rows columns LCD PCF8578 V 4 ...
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... NXP Semiconductors Table 5 to produce the standard multiplex rates. Table 5. Resistors 8.2 Power-on reset At power-on the PCF8578 resets to a defined starting condition as follows: 1. Display blank 2. 1:32 multiplex rate, row mode 3. Start bank 0 selected 4. Data pointer is set address Character mode 6. Subaddress counter is set ...
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... NXP Semiconductors where the values for n are determined by the multiplex rate (1:n). Valid values for n are for 1:8 multiplex for 1:16 multiplex for 1:24 multiplex for 1:32 multiplex Table 6. Bias ratios V 2 ------------- - V oper V 3 ------------- - V oper V 4 ------------- - V oper V 5 ------------- - V oper Table 7. Discrimination ...
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... NXP Semiconductors Fig 6. PCF8578_6 Product data sheet LCD row/column driver for dot matrix graphic displays 1.0 V bias V oper 0.8 0.6 0.4 0 see Table 6. bias function of the multiplex rate bias oper Rev. 06 — 5 May 2009 PCF8578 msa838 oper oper oper ...
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... NXP Semiconductors 8.4 LCD drive mode waveforms ROW LCD COLUMN LCD SYNC ROW LCD COLUMN LCD SYNC ROW LCD COLUMN LCD SYNC ROW LCD COLUMN LCD SYNC Fig 7. LCD row and column waveforms PCF8578_6 Product data sheet LCD row/column driver for dot matrix graphic displays ...
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... NXP Semiconductors ROW 1 R1 (t) ROW 2 R2 (t) COL 1 C1 (t) COL 2 C2 (t) V 0.261 V (t) V state 0.261 0.478 V 0.261 V ( state 2 0.261 V 0.478 (t) = C1(t) R1(t). state1 – on RMS = + ---------------------- - -- - ----------------------- - oper V (t) = C2(t) R2(t). state2 – off RMS ------------------------------ - ----------------------- - = oper Fig 8. LCD drive mode waveforms for 1:8 multiplex rate ...
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... NXP Semiconductors ROW ( LCD ROW ( LCD COL ( LCD COL ( LCD V oper 0.2 V oper ( state 1 0.2 V oper V oper V oper 0.6 V oper 0.2 V oper (t) V state 0.2 V oper 0.6 V oper V oper V (t) = C1(t) R1(t). state1 RMS ---------------------- - = ----- - + ------------------------------ oper V (t) = C2(t) R2(t). state2 – off RMS ...
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... NXP Semiconductors 8.5 Oscillator 8.5.1 Internal clock The clock signal for the system may be generated by the internal oscillator and prescaler. The frequency is determined by the value of the resistor R normal use a value of 330 k is recommended. The clock signal, for cascaded PCF8579s, is output at CLK and has a frequency of ...
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... NXP Semiconductors 8.7 Row and column drivers Outputs and C32 to C39 are fixed as row and column drivers respectively. The remaining 24 outputs R8/C8 to R31/C31 are programmable and may be configured (in blocks either row or column drivers. The row select signal is produced sequentially at each output from the number defined by the multiplex rate (see Table 4). In mixed mode the remaining outputs are confi ...
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... NXP Semiconductors 8.8.4 Acknowledge The number of data bytes transferred between the START and STOP conditions from transmitter to receiver is unlimited. Each data byte of eight bits is followed by one acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter, whereas the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed must generate an acknowledge after the reception of each byte ...
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... NXP Semiconductors BY TRANSMITTER Fig 14. Acknowledgement on the I 2 8.8.5 I C-bus controller 2 The I C-bus controller detects the I data bytes. It performs the conversion of the data input (serial-to-parallel) and the data output (parallel-to-serial). The PCF8578 acts mixed mode, and as a slave receiver in row mode. A slave device cannot control bus communication. 8.8.6 Input fi ...
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... NXP Semiconductors slave address byte a. Master transmits to slave receiver (WRITE mode) slave address Master reads after sending command string (write commands; read data) slave address Master reads slave immediately after sending slave address (READ mode) 2 Fig 15. I C-bus protocol In READ mode, indicated by setting the read/write bit HIGH, data bytes may be read from the RAM following the slave address acknowledgement ...
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... NXP Semiconductors master receiver must signal an end of data to the slave transmitter, by not generating an acknowledge on the last byte clocked out of the slave. The slave transmitter then leaves the data line HIGH, enabling the master to generate a STOP condition (P). Display bytes are written into, or read from the RAM at the address specified by the data pointer and subaddress counter ...
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... NXP Semiconductors Table 10. Bit 7 Fig 16. General information of command byte Table 11. Bit PCF8578_6 Product data sheet LCD row/column driver for dot matrix graphic displays C bit description Symbol Value Description C continue bit 0 last control byte in the transfer; next byte will be regarded as display data 1 control bytes continue ...
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... NXP Semiconductors Table 12. Bit [1] Useful for scrolling, pseudo-motion and background preparation of new display content. Table 13. Bit [1] Values shown in decimal. Table 14. Bit [1] See operation code for set-start-bank in [2] Values shown in decimal. PCF8578_6 Product data sheet LCD row/column driver for dot matrix graphic displays ...
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... NXP Semiconductors Table 15. Bit [1] Values shown in decimal. 8.11 RAM access LSB MSB Fig 17. RAM addressing scheme RAM operations are only possible when the PCF8578 is in mixed mode. In this event its hardware subaddress is internally fixed at 0000 and the hardware subaddresses of any PCF8579 used in conjunction with the PCF8578 must start at 0001. ...
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PCF8578/PCF8579 driver 1 RAM 4 bytes 40-bits 1 byte bytes ...
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DEVICE SELECT: subaddress 12 RAM ACCESS: character mode bank 1 LOAD X-ADDRESS: X-address = slave address DEVICE SELECT ...
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... NXP Semiconductors 8.12 Display control The display is generated by continuously shifting rows of RAM data to the dot matrix LCD via the column outputs. The number of rows scanned depends on the multiplex rate set by bits M[1:0] of the set-mode command. bank 0 bank 1 bank 2 bank 3 1:32 multiplex rate and start bank = 2. ...
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... NXP Semiconductors The display status (all dots on or off and normal or inverse video) is set by the bits E[1:0] of the set-mode command. For bank switching, the RAM bank corresponding to the top of the display is set by the bits B[1:0] of the set-start-bank command. This is shown in Figure 20 ...
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... NXP Semiconductors 10. Static characteristics Table 17. Static characteristics LCD Symbol Parameter Supplies V supply voltage DD V LCD supply voltage LCD I supply current DD V power-on reset voltage POR Logic V LOW-level input voltage IL V HIGH-level input voltage IH I LOW-level output current OL I HIGH-level output current ...
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... NXP Semiconductors 11. Dynamic characteristics Table 18. Dynamic characteristics All timing values are referenced 3 LCD DD DD Symbol Parameter f clock frequency clk t SYNC propagation delay PD(SYNC_N) t driver propagation delay PD(drv C-bus f SCL clock frequency SCL t spike pulse width w(spike) t bus free time between a STOP ...
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... NXP Semiconductors R31/C31 to R8/C8 and Fig 21. Driver timing waveforms SDA SCL SDA Fig 22. I PCF8578_6 Product data sheet LCD row/column driver for dot matrix graphic displays CLK SYNC t PD(SYNC_N) C39 to C32 BUF LOW t HD;STA 2 C-bus timing waveforms Rev. 06 — 5 May 2009 ...
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R8/ R9/ R10/ R11/ R12/ R13 C10 C11 C12 C13 PCF8578 V SA0 SS OSC SDA SCL SYNC CLK TEST ...
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... NXP Semiconductors R15 (Using 1:16 mux, the first character data must be loaded in bank 0 and 1 starting at byte number 16) 0 DISPLAY RAM PCF8578 1-byte Fig 24. Segment driver application for up to 384 segments PCF8578_6 Product data sheet LCD row/column driver for dot matrix graphic displays ...
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rows 3 PCF8578 4 unused columns (ROW MODE SA0 LCD V LCD V ...
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rows rows PCF8578 4 (ROW MODE) unused columns SA0 ...
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3 rows PCF8578 V 4 (ROW MODE) unused columns SA0 ...
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SCL DD V SDA LCD R0 R ext(OSC 3 n.c. n.c. PCF8578 R31/C31 Fig 28. Example of wiring, single screen with 1:32 multiplex rate (PCF8578 in row driver mode) LCD DISPLAY ...
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... NXP Semiconductors 13. Package outline VSO56: plastic very small outline package; 56 leads pin 1 index 1 e DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT max. 0.3 3.0 mm 3.3 0.25 0.1 2.8 0.012 0.12 inches 0.01 0.13 0.004 0.11 Notes 1. Plastic or metal protrusions of 0.3 mm (0.012 inch) maximum per side are not included. ...
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... NXP Semiconductors LQFP64: plastic low profile quad flat package; 64 leads; body 1 pin 1 index DIMENSIONS (mm are the original dimensions) A UNIT max. 0.20 1.45 1.6 mm 0.25 0.05 1.35 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION IEC SOT314-2 136E10 Fig 30 ...
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... NXP Semiconductors TQFP64: plastic thin quad flat package; 64 leads; body 1 pin 1 index DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 1.05 1.2 mm 0.25 0.05 0.95 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION IEC SOT357-1 137E10 Fig 31 ...
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... NXP Semiconductors 14. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description” . 14.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits ...
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... NXP Semiconductors 14.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • ...
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... NXP Semiconductors Fig 32. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description” . 15. Abbreviations Table 21. Acronym CMOS LCD LSB MSB MSL PCB POR RC RAM RMS SCL SDA ...
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... Release date PCF8578_6 20090505 • Modifications: The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Legal texts have been adapted to the new company name where appropriate. • Added package type TQFP64 (PCF8578HT/1) • ...
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... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...
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... NXP Semiconductors 19. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 5 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 6 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 7 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 7.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 7.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 7 8 Functional description . . . . . . . . . . . . . . . . . . . 8 8.1 Display configurations 8.2 Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . 10 8.3 Multiplexed LCD bias generation . . . . . . . . . . 10 8.4 LCD drive mode waveforms ...