MIC2592B-2BTQ Micrel Inc, MIC2592B-2BTQ Datasheet
MIC2592B-2BTQ
Specifications of MIC2592B-2BTQ
Available stocks
Related parts for MIC2592B-2BTQ
MIC2592B-2BTQ Summary of contents
Page 1
... General Description The MIC2592B is a dual-slot power controller supporting the power distribution requirements for Peripheral Component Interconnect Express (PCI Express) Hot-Plug compliant systems. The MIC2592B provides complete power control support for two PCI Express slots, including the 3.3VAUX defi ned by the PCI Express standards. Support for 12V, 3.3V, and 3 ...
Page 2
... R may vary 12VGATE[A/B] 3VGATE[A/B] depending upon the the external MOSFETs. # These components are not required for MIC2592B operation but can be implemented for GATE output slew rate control (application specific) ¥ Bold lines indicate high current paths PCI Express Connector PCI ...
Page 3
Pin Confi guration /FAULTA CFILTERA 12VGATEA GPI_A0 12VINA /PWRGDA 12VSENSEA /FORCE_ONA 12VOUTA VSTBYA 3VINA Slot A Interface March 2005 Hot-Plug Control Interface ...
Page 4
... These two pins must ultimately connect to each other as close as possible at the MIC2592B controller in order to eliminate any IR drop between these the MIC2592B controller in order to eliminate any IR drop between these the MIC2592B controller in order to eliminate any IR drop between these the MIC2592B controller in order to eliminate any IR drop between these pins ...
Page 5
... VSTBY[A/B] rises above its UVLO threshold. Both pins must be externally connected together at the MIC2592B threshold. Both pins must be externally connected together at the MIC2592B threshold. Both pins must be externally connected together at the MIC2592B threshold. Both pins must be externally connected together at the MIC2592B controller. controller. controller. ...
Page 6
Pin Description (continued) Pin Number Pin Number Pin Number Pin Name Pin Name Pin Name ...
Page 7
Absolute Maximum Ratings Supply Voltages 12VIN[A/B] ............................................................... 14V 3VIN[A/B], VSTBY[A/B] ............................................... 7V Any Logic Pin ......................... –0.5V (min) to 3.6V (max) Output Current (/FAULT[A/B], /INT, SDA) ................... 10mA Power Dissipation ..................................... Internally Limited Lead Temperature (IR Refl ow, Peak Temperature) ...
Page 8
... Min Min Min Min Min Typ Typ Typ Typ Typ Typ Typ THILIMIT THILIMIT THILIMIT 4 MIC2592B-2BTQ MIC2592B-2BTQ 90 100 100 MIC2592B-3BTQ MIC2592B-3BTQ 135 150 150 MIC2592B-5BTQ MIC2592B-5BTQ MIC2592B-5BTQ MIC2592B-5BTQ MIC2592B-5BTQ MIC2592B-5BTQ MIC2592B-5BTQ Disabled Disabled Disabled Disabled Disabled Disabled Disabled 0.35 0.35 0.35 ...
Page 9
... STBYA STBYB MIC2592B-2BTQ MIC2592B-2BTQ MIC2592B-2BTQ MIC2592B-2BTQ MIC2592B-2BTQ MIC2592B-2BTQ MIC2592B-2BTQ FILTER ( –V = 140mV IN SENSE MIC2592B-2BTQ MIC2592B-2BTQ MIC2592B-2BTQ MIC2592B-2BTQ MIC2592B-2BTQ MIC2592B-2BTQ MIC2592B-2BTQ FILTER ( –V = 140mV IN SENSE MIC2592B-2BTQ MIC2592B-2BTQ MIC2592B-2BTQ MIC2592B-2BTQ MIC2592B-2BTQ MIC2592B-2BTQ MIC2592B-2BTQ limit to /FAULT[A/B] output limit to /FAULT[A/B] output limit to /FAULT[A/B] output limit to /FAULT[A/B] output ...
Page 10
Timing Diagrams SCL SDA Data In SDA Data Out V – SENSE V THFAST V THILIMIT 12VGATE 0V t OFF(12V) Figure 2. 12V Current Limit Response Timing Must Trip I AUX(THRESH) May Not Trip OUT(AUX) ...
Page 11
... TEMPERATURE (°C) CFILTER Threshold vs. Temperature 1.30 1.29 1.28 1.27 1.26 1.25 1.24 1.23 1.22 1.21 1.20 1.20 1. TEMPERATURE (°C) Current Limit (Fast Threshold) vs. Temperature MIC2592B-2BTQ 120 115 110 105 12V 100 TEMPERATURE (° GATE vs. Temperature 12.00 11.75 11.50 11.25 11.00 10.75 10 ...
Page 12
... VSTBYA AUXENA MIC2592B ONA /FAULTA CFILTERA GND (Additional pins omitted for clarity - Slot A shown only) MIC2592B Test Circuit 12 V On-Resistance AUX (R ) vs. Temperature DS(ON) 400 350 300 250 200 150 100 ...
Page 13
Functional Characteristics Turn-On Response Slot A TIME (2.5ms/div.) 3V Overcurrent Fault Response R = 0.4Ω LOAD Slot A TIME (5ms/div.) Auxiliary Overcurrent Fault Response R = 3.3Ω LOAD Overcurrent on Slot B TIME (5ms/div.) March 2005 GATE Output Turn-On Response ...
Page 14
Functional Characteristics cont. 3V Undervoltage Fault Response +3VIN /FAULT +12VIN VSTBY MAIN(12V and 3.3V) Supplies ENABLED Slot A TIME (500µs/div.) 3V Ouput Discharge Response V UV(3V) TIME (25ms/div.) March 2005 V UVLO(3V) Output disabled by ON pin C = 1000µF ...
Page 15
... ON/OFF 100mV* ON/OFF 100mV* Overcurrent Detection V STBY(REF) I REF Current Mirror CFILTER[A/B] RFILTER[A&B] /FORCE_ON[A/B] GPI_[A0/B0] * MIC2592B-3BTQ fast threshold is 150mV MIC2592B-5BTQ fast threshold is disabled Contact factory for availabilty March 2005 ON[A/B] AUX[A/B] Power-on VSTBY Reset UVLO 250s Bandgap Reference V REF 12V ...
Page 16
... Suffi cient input bulk capacitance should be used to prevent the supply from "drooping", causing VSTBY[A/B] to fall below the UVLO threshold. Also, decoupling capacitors should be placed at each of the MIC2592B inputs in order to fi lter high frequency noise transients. V STBY ...
Page 17
... Table 1. 3.3V and 12V Output Slew-Rate Selection for ] until the associated Power-Down Cycle When one or more PCI slots are disabled via the MIC2592B output control pins, ON[A/B] or AUXEN[A/B], the output volt- age for each supply will discharge as a function of the RC time constant produced by the controller’s internal resistance ...
Page 18
... VSTBY[A/B] is present. Prior to standby mode, ONA and ONB (or the Control Registers' MAINA and MAINB bits) inputs should be deasserted or the MIC2592B will assert /FAULT[A/B] and /INT (if inter- rupts are enabled) output signals undervoltage condi- tion on the MAIN supply inputs is detected. ...
Page 19
... Once the input supplies are above their respective UVLO thresholds, the Hot-Plug Interface can be utilized for power control by enabling the control input pins (AUXEN[A/B] and ON[A/B]) for each slot. In order for the MIC2592B to switch on the VAUX supply for either slot, the AUXEN[A/B] control must be enabled after the power-on-reset delay, t March 2005 cally, 250µ ...
Page 20
... Byte Read from MIC2592B MIC2592B Device Address DATA R/W = READ ACKNOWLEDGE NOT ACKNOWLEDGE START CLK Master to device transfer, i.e., DATA driven by master. Figure 12. RECEIVE_BYTE Protocol FLT * Data Byte to MIC2592B ACKNOWLEDGE STOP Data Read From MIC2592B R/W = READ ACKNOWLEDGE NOT ACKNOWLEDGE Device to master transfer, i ...
Page 21
... Read_Byte operation is similar, but is a composite write and read operation: the host fi rst sends the device’s target address followed by the command byte write operation. A new “Start” bit must then be sent to the MIC2592B, followed by a MIC2592B Register Set and Programmer’s Model Target Register ...
Page 22
Detailed Register Descriptions Control Register, Slot A (CNTRLA) 8-Bits, Read/Write D[7] D[7] D[7] D[7] D[7] D[7] D[7] D[7] D[6] D[6] D[6] D[6] D[6] D[6] D[6] D[6] read-only read-only read-only read-only read-only read-only read-only read-only read-only read-only read-only read-only read-only read-only ...
Page 23
Control Register, Slot B (CNTRLB) 8-Bits, Read/Write D[7] D[7] D[7] D[7] D[7] D[7] D[7] D[7] D[6] D[6] D[6] D[6] D[6] D[6] D[6] D[6] read-only read-only read-only read-only read-only read-only read-only read-only read-only read-only read-only read-only read-only read-only read-only read-only AUXBPG ...
Page 24
... If an overcurrent has occurred on both a MAIN output and the VAUX output of slot A, both ONA and AUXENA of the slot must go low to reset FAULTA. 2. Neither the FAULTA bits nor the /FAULTA pins are active when the MIC2592B power paths are controlled by the System Management Interface. When using SMI power path control, AUXENA and ONA pins for that slot must be tied to GND. March 2005 ...
Page 25
... If an overcurrent has occurred on both a MAIN output and the VAUX output of slot B, both ONB and AUXENB of the slot must go low to reset FAULTB. 2. Neither the FAULTB bits nor the /FAULTB pins are active when the MIC2592B power paths are controlled by the System Management Interface. When using SMI power path control, the AUXENB and ONB pins for that slot must be tied to GND. 3:. ...
Page 26
... The 1 = /INT generation is disabled. The 1 = /INT generation is disabled. The MIC2592B does not participate in the SMBus MIC2592B does not participate in the SMBus MIC2592B does not participate in the SMBus Alert Response Address (ARA) protocol Alert Response Address (ARA) protocol ...
Page 27
... However, individual system analysis should be used to de- termine if fi ltering is necessary and to select the appropriate cutoff frequency for each specifi c application. Other Layout Considerations 56.7mV Figure suggested PCB layout diagram for the MIC2592B = power traces, Kelvin sense connections, and capacitor com SENSE(NOM) ponents ...
Page 28
... Power Trace From V IN PCB Track Width: 0.03" per Ampere using 1oz Cu Signal Trace to MIC2592B VIN Pin Note: Each SENSE lead trace shall be balanced for best performance & equal length/equal aspect ratio. Figure 13. 4-Wire Kelvin Sense Connections for R SENSE March 2005 ...
Page 29
Current Flow to the Load W Via to GND Plane Via to signal plane (GATE pin connection) ***C FILTER W - DRAWING IS NOT TO SCALE AND NOT ALL PINS SHOWN FOR CLARITY- *See Table 4 for part numbers and ...
Page 30
MOSFET and Sense Resistor Vendors Device types, part numbers, and manufacturer contact infor- mation for power MOSFETs and sense resistors are provided in Table 4. Some of the recommended MOSFETs include a metal (tab) heat sink on the bottom side ...
Page 31
Package Information MICREL, INC. 1849 FORTUNE DRIVE SAN JOSE, CA 95131 USA + 1 (408) 944-0800 TEL The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel ...