HCPL-316J-000E Avago Technologies US Inc., HCPL-316J-000E Datasheet - Page 10

OPTOCOUPLER GATE DRV 2A 16-SOIC

HCPL-316J-000E

Manufacturer Part Number
HCPL-316J-000E
Description
OPTOCOUPLER GATE DRV 2A 16-SOIC
Manufacturer
Avago Technologies US Inc.
Datasheet

Specifications of HCPL-316J-000E

Configuration
High-Side
Package / Case
16-SOIC (0.300", 7.5mm Width)
Input Type
Differential
Delay Time
300ns
Current - Peak
2.5A
Number Of Configurations
1
Number Of Outputs
1
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
-40°C ~ 100°C
Mounting Type
Surface Mount
Fall Time
0.1 us
Rise Time
0.1 us
Isolation Voltage
6000 Vrms
Maximum Power Dissipation
1200 mW
Maximum Operating Temperature
+ 100 C
Minimum Operating Temperature
- 40 C
No. Of Channels
1
Optocoupler Output Type
Gate Drive
Input Current
22mA
Output Voltage
30V
Opto Case Style
SOIC
No. Of Pins
16
Common Mode Ratio
15 KV/uS
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
High Side Voltage - Max (bootstrap)
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
516-1478-5

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HCPL-316J-000E
Manufacturer:
KOITECH
Quantity:
713
Part Number:
HCPL-316J-000E
Manufacturer:
AVAGO
Quantity:
21 000
Part Number:
HCPL-316J-000E
Manufacturer:
AVAGO/安华高
Quantity:
20 000
Switching Specifications (AC)
Unless otherwise noted, all typical values at T
all Minimum/Maximum specifications are at Recommended Operating Conditions.
Parameter
V
Propagation Delay Time
V
Propagation Delay Time
Pulse Width Distortion
Propagation Delay Difference
Between Any Two Parts
10% to 90% Rise Time
90% to 10% Fall Time
DESAT Sense to 90% V
DESAT Sense to 10% V
DESAT Sense to Low Level FAULT
Signal Delay
DESAT Sense to DESAT Low
Propagation Delay
RESET to High Level FAULT Signal
Delay
RESET Signal Pulse Width
UVLO to V
UVLO to V
Output High Level Common Mode
Transient Immunity
Output Low Level Common Mode
Transient Immunity
10
IN
IN
to High Level Output
to Low Level Output
OUT
OUT
High Delay
Low Delay
OUT
OUT
Delay
Delay
t
t
PWD
(t
PDD
t
t
t
t
t
t
t
PW
t
t
|CM
|CM
PLH
PHL
r
f
DESAT(90%)
DESAT(10%)
DESAT(FAULT)
DESAT(LOW)
RESET(FAULT)
UVLO ON
UVLO OFF
PHL
Symbol
RESET
H
L
|
- t
|
PLH
A
)
= 25°C, V
Min.
0.10
0.10
-0.30
-0.35
3
0.1
15
15
CC1
Typ.
0.30
0.32
0.02
0.1
0.1
0.3
2.0
1.8
0.25
7
4.0
6.0
30
30
= 5 V, and V
Max.
0.50
0.50
0.30
0.35
0.5
3.0
5
20
CC2
Units
μs
kV/μs
- V
EE
= 30 V, V
Rg = 10 Ω
Cg = 10 nF,
f = 10 kHz,
Duty Cycle = 50%
Rg = 10 Ω,
Cg = 10 nF
V
V
ramp
T
V
V
T
V
V
Test Conditions
A
A
CC2
CC2
CM
CC2
CM
CC2
= 25°C,
= 25°C,
= 1500 V,
= 1500 V,
- V
= 1.0 ms
= 30 V
= 30 V
EE
E
- V
= 30 V
EE
= 0 V;
17,18,19,
20,21,22,
45,54,55
45
23,56
24,28,
46,56
25,47,
56
56
26,27,
56
49
50,51,
52,53
Fig.
Note
15
16,17
17,18
19
20
21
22
13
14
23
24

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