IC MOSFET DVR SYNC BUCK 10-DFN

ISL6594BCRZ-T

Manufacturer Part NumberISL6594BCRZ-T
DescriptionIC MOSFET DVR SYNC BUCK 10-DFN
ManufacturerIntersil
ISL6594BCRZ-T datasheet
 

Specifications of ISL6594BCRZ-T

ConfigurationHigh and Low Side, SynchronousInput TypePWM
Delay Time10.0nsCurrent - Peak1.25A
Number Of Configurations1Number Of Outputs2
High Side Voltage - Max (bootstrap)36VVoltage - Supply10.8 V ~ 13.2 V
Operating Temperature0°C ~ 85°CMounting TypeSurface Mount
Package / Case10-DFNLead Free Status / RoHS StatusLead free / RoHS Compliant
Other namesISL6594BCRZ-T  
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desired frequency for the selected MOSFETs. The total gate
drive power losses due to the gate charge of MOSFETs and
the driver’s internal circuitry and their corresponding average
driver current can be estimated with Equations 2 and 3,
respectively:
P
=
P
+
P
+
I
VCC
Qg_TOT
Qg_Q1
Qg_Q2
Q
2
Q
UVCC
G1
-------------------------------------- - f
P
=
N
Qg_Q1
SW
V
GS1
2
Q
LVCC
G2
------------------------------------- - f
P
=
N
Qg_Q2
SW
V
GS2
Q
UVCC N
Q
LVCC N
G1
Q1
G2
I
----------------------------------------------------- -
---------------------------------------------------- -
=
+
DR
V
V
GS1
GS2
where the gate charge (Q
and Q
G1
G2
particular gate to source voltage (V
GS1
corresponding MOSFET datasheet; I
Q
quiescent current with no load at both drive outputs; N
and N
are number of upper and lower MOSFETs,
Q2
respectively; UVCC and LVCC are the drive voltages for
both upper and lower FETs, respectively. The I
product is the quiescent power of the driver without
capacitive load and is typically 116mW at 300kHz.
The total gate drive power losses are dissipated among the
resistive components along the transition path. The drive
resistance dissipates a portion of the total gate drive power
losses, the rest will be dissipated by the external gate
resistors (R
and R
) and the internal gate resistors
G1
G2
(R
and R
) of MOSFETs. Figures 3 and 4 show the
GI1
GI2
typical upper and lower gate drives turn-on transition path.
The power dissipation on the driver can be roughly
estimated as shown in Equation 4:
P
P
P
I
VCC
=
+
+
DR
DR_UP
DR_LOW
Q
R
R
HI1
LO1
P
--------------------------------------
--------------------------------------- -
=
+
DR_UP
R
R
R
R
+
+
HI1
EXT1
LO1
EXT1
R
R
HI2
LO2
P
--------------------------------------
--------------------------------------- -
=
+
DR_LOW
R
R
R
R
+
+
HI2
EXT2
LO2
R
GI1
R
R
-------------
R
=
+
=
EXT1
G1
EXT2
N
Q1
8
ISL6594A, ISL6594B
UVCC
(EQ. 2)
Q1
FIGURE 3. TYPICAL UPPER-GATE DRIVE TURN-ON PATH
Q2
Q2
f
I
+
SW
Q
(EQ. 3)
) is defined at a
and V
) in the
GS2
is the driver’s total
Q1
VCC
Q*
FIGURE 4. TYPICAL LOWER-GATE DRIVE TURN-ON PATH
Layout Considerations
For heat spreading, place copper underneath the IC whether
it has an exposed pad or not. The copper area can be
extended beyond the bottom area of the IC and/or
connected to buried copper plane(s) with thermal vias. This
combination of vias for vertical heat escape, extended
copper plane, and buried planes for heat spreading allows
the IC to achieve its full thermal potential.
Place each channel power component as close to each
other as possible to reduce PCB copper losses and PCB
(EQ. 4)
parasitics: shortest distance between DRAINs of upper FETs
and SOURCEs of lower FETs; shortest distance between
P
DRAINs of lower FETs and the power ground. Thus, smaller
Qg_Q1
---------------------
2
amplitudes of positive and negative ringing are on the
switching edges of the PHASE node. However, some space
P
in between the power components is required for good
Qg_Q2
---------------------
airflow. The traces from the drivers to the FETs should be
2
EXT2
kept short and wide to reduce the inductance of the traces
and to promote clean drive signals.
R
GI2
R
-------------
+
G2
N
Q2
BOOT
C
GD
R
G
HI1
R
R
LO1
R
GI1
G1
C
GS
PHASE
LVCC
C
GD
R
G
HI2
R
R
R
LO2
GI2
G2
C
GS
S
D
C
DS
Q1
S
D
C
DS
Q2
FN9157.5
December 3, 2007