IRS2330DJPBF International Rectifier, IRS2330DJPBF Datasheet - Page 21

IC DVR 3-PHASE BRIDGE PLCC44

IRS2330DJPBF

Manufacturer Part Number
IRS2330DJPBF
Description
IC DVR 3-PHASE BRIDGE PLCC44
Manufacturer
International Rectifier
Datasheet

Specifications of IRS2330DJPBF

Configuration
3 Phase Bridge
Input Type
Inverting
Delay Time
500ns
Current - Peak
250mA
Number Of Configurations
1
Number Of Outputs
3
High Side Voltage - Max (bootstrap)
600V
Voltage - Supply
10 V ~ 20 V
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
IRS2330DJPBF
Manufacturer:
International Rectifier
Quantity:
10 000
IRS233(0,2)(D)(S&J)PbF
Figure 25: Parasitic Elements
Figure 26: V
positive
Figure 27: V
negative
S
S
In a typical motor drive system, dV/dt is typically designed to be in the range of 3-5 V/ns. The negative V
transient voltage
S
can exceed this range during some events such as short circuit and over-current shutdown, when di/dt is greater than in
normal operation.
International Rectifier’s HVICs have been designed for the robustness required in many of today’s demanding applications. An
indication of the IRS233(0,2)(D)’s robustness can be seen in Figure 28, where there is represented the IRS233(0,2)(D) Safe
Operating Area at V
=15V based on repetitive negative V
spikes. A negative V
transient voltage falling in the grey area
BS
S
S
(outside SOA) may lead to IC permanent damage; viceversa unwanted functional anomalies or permanent damage to the IC
do not appear if negative Vs transients fall inside SOA.
At V
=15V in case of -V
transients greater than -16.5 V for a period of time greater than 50 ns; the HVIC will hold by design
BS
S
the high-side outputs in the off state for 4.5 μs.
Figure 28: Negative V
transient SOA for IRS233(0,2)(D)
S
Even though the IRS233(0,2)(D) has been shown able to handle these large negative V
transient conditions, it is highly
S
recommended that the circuit designer always limit the negative V
transients as much as possible by careful PCB layout and
S
component use.
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21

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