ISL6596CRZ Intersil, ISL6596CRZ Datasheet - Page 8

• Manufacturer Part Number: ISL6596CRZ
• Description: IC MOSFET DRVR SYNC BUCK 10-DFN
• Manufacturer: Intersil

Specifications of ISL6596CRZ

• Configuration: High and Low Side, Synchronous
• Input Type: PWM
• Delay Time: 19ns
• Current - Peak: 2A
• Number Of Configurations: 1
• Number Of Outputs: 2
• High Side Voltage - Max (bootstrap): 36V
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 10-DFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Power Dissipation
Package power dissipation is mainly a function of the
switching frequency (F
external gate resistance, and the selected MOSFET’s
internal gate resistance and total gate charge. Calculating
the power dissipation in the driver for a desired application is
critical to ensure safe operation. Exceeding the maximum
allowable power dissipation level will push the IC beyond the
maximum recommended operating junction temperature of
+125°C. The maximum allowable IC power dissipation for
the SO8 package is approximately 800mW at room
temperature, while the power dissipation capacity in the DFN
package, with an exposed heat escape pad, is much higher.
See “Layout Considerations” on page 9 for thermal transfer
improvement suggestions. When designing the driver into an
application, it is recommended that the following calculation
is used to ensure safe operation at the desired frequency for
the selected MOSFETs. The total gate drive power losses
due to the gate charge of MOSFETs and the driver’s internal
circuitry and their corresponding average driver current can
be estimated with Equations 2 and 3, respectively:
where the gate charge (Q
particular gate to source voltage (V
corresponding MOSFET datasheet; I
quiescent current with no load at both drive outputs; N
and N
respectively. The I
the driver without capacitive load and is typically negligible.
P
P
P
I
VCC
Qg_TOT
Qg_Q1
Qg_Q2
=
Q2
⎛
⎜
⎝
=
=
Q
----------------------------- -
are the number of upper and lower MOSFETs,
=
G1
Q
---------------------------------- F
Q
---------------------------------- F
V
P
G1
G2
GS1
Qg_Q1
•
V
V
N
•
GS1
•
GS2
Q1
VCC
VCC
Q
+
+
V
Q
----------------------------- -
P
2
2
CC
SW
Qg_Q2
G2
•
•
V
GS2
product is the quiescent power of
G1
SW
SW
), the output drive impedance, the
•
N
Q2
and Q
•
•
+
8
N
N
I
⎞
⎟
⎠
Q
Q1
Q2
•
•
VCC F
VCC
GS1
G2
Q
) is defined at a
and V
is the driver’s total
•
SW
GS2
+
I
Q
) in the
(EQ. 2)
(EQ. 3)
Q1
ISL6596
The total gate drive power losses are dissipated among the
resistive components along the transition path. The drive
resistance dissipates a portion of the total gate drive power
losses, the rest will be dissipated by the external gate
resistors (R
interfering with the operation shoot-through protection
circuitry) and the internal gate resistors (R
MOSFETs. Figures 3 and 4 show the typical upper and lower
gate drives turn-on transition path. The power dissipation on
the driver can be roughly estimated as:
P
P
P
R
DR
DR_UP
DR_LOW
EXT2
FIGURE 4. TYPICAL LOWER-GATE DRIVE TURN-ON PATH
FIGURE 3. TYPICAL UPPER-GATE DRIVE TURN-ON PATH
VCC
=
P
=
VCC
DR_UP
=
R
=
⎛
⎜
⎝
G1
G1
--------------------------------------
R
⎛
⎜
⎝
R
HI1
--------------------------------------
R
R
+
and R
LO2
HI2
R
HI2
R
+
R
-------------
R
N
LO1
HI1
+
P
GI1
HI1
R
Q1
DR_LOW
R
+
HI2
GND
EXT1
R
LGATE
G2
UGATE
PHASE
EXT2
BOOT
, should be a short to avoid
+
+
+
--------------------------------------- -
R
I
LO1
--------------------------------------- -
R
R
R
Q
LO2
G2
EXT2
R
•
R
G
G1
VCC
+
LO1
R
G
R
+
LO2
R
C
EXT1
R
GI2
R
GD
=
C
EXT2
C
GI1
GD
R
GS
C
G2
GS
⎞
⎟
⎠
GI1
•
⎞
⎟
⎠
S
+
P
---------------------
•
S
R
-------------
N
Qg_Q1
P
---------------------
and R
GI2
Qg_Q2
Q2
2
D
January 22, 2010
2
D
Q2
C
GI2
Q1
DS
C
FN9240.1
(EQ. 4)
DS
) of