LM5100AMX/NOPB National Semiconductor, LM5100AMX/NOPB Datasheet

IC DVR HALF-BRIDGE HV 8-SOIC

LM5100AMX/NOPB

Manufacturer Part Number
LM5100AMX/NOPB
Description
IC DVR HALF-BRIDGE HV 8-SOIC
Manufacturer
National Semiconductor
Datasheet
1.LM5101CSDNOPB.pdf (18 pages)

Specifications of LM5100AMX/NOPB

Configuration
High and Low Side, Synchronous
Input Type
Non-Inverting
Delay Time
20ns
Current - Peak
3A
Number Of Configurations
1
Number Of Outputs
2
High Side Voltage - Max (bootstrap)
118V
Voltage - Supply
9 V ~ 14 V
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Package / Case
8-SOIC (3.9mm Width)
Number Of Drivers
2
Driver Configuration
Non-Inverting
Driver Type
High and Low Side
Input Logic Level
CMOS
Rise Time
430ns
Fall Time
260ns
Propagation Delay Time
20ns
Operating Supply Voltage (max)
14V
Peak Output Current
3mA
Operating Supply Voltage (min)
9V
Turn Off Delay Time
1ns
Turn On Delay Time (max)
1ns
Operating Temp Range
-40C to 125C
Operating Temperature Classification
Automotive
Mounting
Surface Mount
Pin Count
8
Package Type
SOIC N
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
LM5100AMX

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© 2010 National Semiconductor Corporation
3A, 2A and 1A High Voltage High-Side and Low-Side Gate
Drivers
General Description
The LM5100A/B/C and LM5101A/B/C High Voltage Gate
Drivers are designed to drive both the high-side and the low-
side N-Channel MOSFETs in a synchronous buck or a half-
bridge configuration. The floating high-side driver is capable
of operating with supply voltages up to 100V. The “A” versions
provide a full 3A of gate drive while the “B” and “C” versions
provide 2A and 1A respectively. The outputs are indepen-
dently controlled with CMOS input thresholds (LM5100A/B/C)
or TTL input thresholds (LM5101A/B/C). An integrated high
voltage diode is provided to charge the high-side gate drive
bootstrap capacitor. A robust level shifter operates at high
speed while consuming low power and providing clean level
transitions from the control logic to the high-side gate driver.
Under-voltage lockout is provided on both the low-side and
the high-side power rails. These devices are available in the
standard SOIC-8 pin, PSOP-8 pin and the LLP-10 pin pack-
ages. The LM5100C and LM5101C are also available in
eMSOP-8 package. The LM5101A is also available in LLP-8
pin package.
Features
■
■
Simplified Block Diagram
Drives both a high-side and low-side N-Channel
MOSFETs
Independent high and low driver logic inputs
202031
LM5100A/B/C
LM5101A/B/C
FIGURE 1.
■
■
■
■
■
■
■
Typical Applications
■
■
■
■
■
Package
■
■
■
■
■
Bootstrap supply voltage up to 118V DC
Fast propagation times (25 ns typical)
Drives 1000 pF load with 8 ns rise and fall times
Excellent propagation delay matching (3 ns typical)
Supply rail under-voltage lockout
Low power consumption
Pin compatible with HIP2100/HIP2101
Current Fed push-pull converters
Half and Full Bridge power converters
Synchronous buck converters
Two switch forward power converters
Forward with Active Clamp converters
SOIC-8
PSOP-8
LLP-8 (4 mm x 4 mm)
LLP-10 (4 mm x 4 mm)
eMSOP-8
20203103
August 31, 2010
www.national.com

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LM5100AMX/NOPB Summary of contents

Page 1

... Features ■ Drives both a high-side and low-side N-Channel MOSFETs ■ Independent high and low driver logic inputs Simplified Block Diagram © 2010 National Semiconductor Corporation LM5100A/B/C LM5101A/B/C ■ Bootstrap supply voltage up to 118V DC ■ Fast propagation times (25 ns typical) ■ ...

Page 2

Input/Output Options Part Number LM5100A LM5101A LM5100B LM5101B LM5100C LM5101C Connection Diagrams www.national.com Input Thresholds CMOS TTL CMOS TTL CMOS TTL 20203101 20203135 20203136 2 Peak Output Current 20203137 20203102 ...

Page 3

Ordering Information Ordering Number Package Type LM5100A/LM5101AM SOIC 8 LM5100A/LM5101AMX SOIC 8 LM5100A/LM5101AMR PSOP 8 LM5100A/LM5101AMRX PSOP 8 LM5100A /LM5101ASD LLP 10 LM5100A/LM5101ASDX LLP 10 LM5100B/LM5101BMA SOIC 8 LM5100B/LM5101BMAX SOIC 8 LM5100B/LM5101BSD LLP 10 LM5100B/LM5101BSDX LLP 10 LM5100C/LM5101CMA SOIC 8 ...

Page 4

Pin Descriptions Pin # SOIC-8 PSOP-8 LLP-8 LLP- ...

Page 5

... Absolute Maximum Ratings If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. VDD to VSS Input LO Output HO Output VSS (Note VSS Electrical Characteristics Limits in standard type are for T = 25°C only; limits in boldface type apply over the junction temperature (T J +125° ...

Page 6

Symbol Parameter I Peak Pulldown Current LM5100A/LM5101A OLL Peak Pulldown Current LM5100B/LM5101B Peak Pulldown Current LM5100C/LM5101C THERMAL RESISTANCE θ Junction to Ambient JA Switching Characteristics Limits in standard type are for T = 25°C only; limits in boldface type apply ...

Page 7

Symbol Parameter t Minimum Input Pulse Width that Changes PW the Output t Bootstrap Diode Reverse Recovery Time I BS Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under ...

Page 8

LM5100A/B Frequency DD Operating Current vs Temperature Quiescent Current vs Supply Voltage www.national.com LM5101A/B/C I 20203109 I HB 20203111 Quiescent Current vs Temperature 20203118 8 vs Frequency DD 20203110 vs Frequency 20203114 20203119 ...

Page 9

Undervoltage Rising Thresholds vs Temperature Bootstrap Diode Forward Voltage LM5101A/B/C Input Threshold vs Temperature Undervoltage Threshold Hysteresis vs Temperature 20203122 LM5100A/B/C Input Threshold vs Temperature 20203115 LM5100A/B/C Input Threshold vs VDD 20203124 9 20203117 20203123 20203125 www.national.com ...

Page 10

LM5101A/B/C Input Threshold vs VDD LM5101A/B/C Propagation Delay vs Temperature LO & HO Gate Drive - Low Level Output Voltage vs Temperature www.national.com LM5100A/B/C Propagation Delay vs Temperature 20203126 LO & HO Gate Drive - High Level Output Voltage vs ...

Page 11

LO & HO Gate Drive - Output Low Voltage vs VDD Timing Diagram 20203132 FIGURE 2. 11 20203104 www.national.com ...

Page 12

Layout Considerations The optimum performance of high and low-side gate drivers cannot be achieved without taking due considerations during circuit board layout. Following points are emphasized. 1. Low ESR / ESL capacitors must be connected close to the IC, between ...

Page 13

Power Dissipation Considerations The total IC power dissipation is the sum of the gate driver losses and the bootstrap diode losses. The gate driver losses are related to the switching frequency (f), output load capac- itance on LO and HO ...

Page 14

Physical Dimensions   Controlling dimension is inch. Values are millimeters. Notes: Unless otherwise specified. 1. Standard lead finish to be 200 microinches/5.08 micrometers minimum lead/tin (solder) on copper. 2. Dimension does not include mold flash. Reference JEDEC ...

Page 15

... Notes: Unless otherwise specified. 1. For solder thickness and composition, see “Solder Information” in the packaging section of the National Semiconductor web page (www.national.com). 2. Maximum allowable metal burr on lead tips at the package edges is 76 microns JEDEC registration as of May 2003. LLP-8 Outline Drawing ...

Page 16

Outline Drawing NS Package Number MUY08A 16 ...

Page 17

Notes 17 www.national.com ...

Page 18

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