MCZ33937AEK Freescale Semiconductor, MCZ33937AEK Datasheet

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... Figure 1. 33937 Simplified Application Diagram * This document contains certain information on a new product. Specifications and information herein are subject to change without notice. © Freescale Semiconductor, Inc., 2008-2009. All rights reserved. ™ technology. Device MCZ33937EK/R2 MCZ33937AEK/R2 33937 VPUMP VSUP PUMP PA_HS_G VPWR PB_HS_G ...

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... Loss of regulation during indeterminate RESET level High Bootstrap initialization current causes reset MCZ33937A Invalid zero length SPI commands cause Framing Errors 33937 2 DEVICE VARIATIONS Significant Device Variations Reference Location Note 2 on page 7 Caution on page 28 Framing Error on page 37 Analog Integrated Circuit Device Data Freescale Semiconductor ...

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... PX_LS CS SI SCLK SO 3 PHASEX + OC_OUT - OVER-CUR. GND(2) COMP. VSS OC_TH AMP_OUT Figure 2. 33937 Simplified Internal Block Diagram Analog Integrated Circuit Device Data Freescale Semiconductor INTERNAL BLOCK DIAGRAM VPWR VLS 5.0 V REG. REG. VDD UV DETECT 3X T-LIM VSUP + 1.4 V DESAT. - COMP CONTROL ...

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... VPWR N/C N/C VLS N/C N/C PA_BOOT PA_HS_G PA_HS_S PA_LS_G PA_LS_S PB_BOOT PB_HS_G PB_HS_S PB_LS_G PB_LS_S PC_BOOT PC_HS_G PC_HS_S PC_LS_G PC_LS_S N/C VLS_CAP GND1 GND0 VSS OC_TH section beginning on page 23. Definition Analog Integrated Circuit Device Data Freescale Semiconductor SUP SUP SUP ...

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... Analog Input 44 PA_LS_S Power Input Analog Integrated Circuit Device Data Freescale Semiconductor Functional Pin Description Formal Name Active low input logic signal enables the High Side Driver for Phase A Phase A High Side Active high input logic signal enables the Low Side Driver for Phase A Phase A Low Side VDD regulator output capacitor connection ...

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... Power supply input for gate drives Voltage Power Device will perform as specified with the Exposed Pad un-terminated Exposed Pad (floating) however recommended that the Exposed Pad be terminated to pin 29 (VSS) and system ground section beginning on page 23. Definition Analog Integrated Circuit Device Data Freescale Semiconductor ...

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... This voltage should not be applied without also taking voltage at HS_S and voltage at PX_LS_S into account. 5. Actual operational limitations may differ from survivability limits. The V greater than 3 insure the output gate drive will maintain a commanded OFF condition on the output. Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS Symbol (3) ...

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... Symbol Value V ESD ±2000 ±1000 ±750 ±300 T -55 to +150 STG T -40 to +150 Note 9 SOLDER = 100 pF 1500 ) and the Charge Device ZAP ZAP Figure 24 and Figure 25 for examples of Analog Integrated Circuit Device Data Freescale Semiconductor Unit V °C °C °C/W °C ...

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... HOLDOFF circuits are active. Recovery is automatic when V LS above this threshold again. A filter delay of approximately 700 ns on the comparator output eliminates responses to spurious transients Analog Integrated Circuit Device Data Freescale Semiconductor - SUP A PWR = 25° ...

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... Typ Max Unit 6.0 10 5.0 9.4 mV 500 900 V 9.5 – – – – 6.0 – 8.5 – 3.0 – 0.5 A – 6.0 – 8.5 – 3.0 – 0.5 V 14.8 16.5 15.4 17 – 18 µA Analog Integrated Circuit Device Data Freescale Semiconductor ...

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... Exceeding the common mode rails on one input CM will not cause a phase inversion on the output. 26. Input resistance is impedance from High Side source and is referenced to V 27. The current sense amplifier is unity gain stable with a phase margin of approximately 45°. See Analog Integrated Circuit Device Data Freescale Semiconductor - PWR SUP A = 25° ...

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... NL T 135 C, unless otherwise noted. Typical A Min Typ Max -80 – +80 – 40 – V -0.2 – – – 0.2 1.0 – – 5.0 – – – – – – 78 – -1.0 – +1.0 Analog Integrated Circuit Device Data Freescale Semiconductor Unit nA pA/° ...

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... The Thermal Warning circuit does not force IC shutdown above this temperature possible to set a bit in the MASK register to generate an interrupt when overtemperature is detected, and the status bit will always indicate if any of the three individual Thermal Warning circuits in the IC sense a fault. Analog Integrated Circuit Device Data Freescale Semiconductor STATIC ELECTRICAL CHARACTERISTICS ...

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... Figure 6. Analog Integrated Circuit Device Data Freescale Semiconductor Unit ms ms kHz V/µ µ ...

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... ON any output FET. This precludes false errors due to BLANK system noise during the switching event. 47. Without considering any offsets such as input offset voltage, internal mismatch and assuming no tolerance error in external resistors. Analog Integrated Circuit Device Data Freescale Semiconductor - ...

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... Analog Integrated Circuit Device Data Freescale Semiconductor Unit µs µs V/µs ° MHz MHz ...

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... Time required for valid output status data to be available on SO pin. 53. Time required for output states data to be terminated at SO pin. 54. Time required to obtain valid data out from SO following the rise of SCLK with 200 pF load. Analog Integrated Circuit Device Data Freescale Semiconductor - PWR SUP = 25° ...

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... SIHOLD MSB MSB out Figure 4. SPI Interface Timing B MUX OUT D CLK CLK D D CLK CLK Q OUT A MUX B Figure 6. Deadtime Control Delays t t LAG SODIS DO (DIS ) LSB out DESATURATION FAULT Q P _HS_G X P _HS_S _LS_G X Analog Integrated Circuit Device Data Freescale Semiconductor ...

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... Px_HS Px_HS _G 50% Px_LS Px_LS_G Figure 7. Driver Turn-On Time and Turn-On Delay 50% Px_HS Px_HS_G Px_ LS Px_LS_G Figure 8. Driver Turn-off Time and Turn-off Delay Analog Integrated Circuit Device Data Freescale Semiconductor 50% 10V t D_ONH t ONH 10V t D_ONL t ONL 1.0V 10V t D_OFFH t OFFH 50% ...

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... ELECTRICAL CHARACTERISTICS TIMING DIAGRAMS To P rotection Circuits Figure 9. Current Amplifier and Input Waveform (V Figure 10. Typical Amplifier Open-loop Gain and Phase Margin vs Frequency 33937 AMP_P + AMP_N R s OC_TH AMP_O UT R FBN Voltage Across sens SENSE Analog Integrated Circuit Device Data Freescale Semiconductor ...

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... Figure 11. Typical Trickle Charge Pump Supply Voltage and Current Margin vs Supply Voltage Trickle Charge Pump Load Margin and Supply Voltage at HS_S=Vsup=14V Figure 12. Typical Voltage and Load Margin For Increasing Junction Temperature HS_S Analog Integrated Circuit Device Data Freescale Semiconductor HS_S/Vsup ( 100 120 Tj ( ELECTRICAL CHARACTERISTICS TIMING DIAGRAMS 12 ...

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... Figure 13. Typical Voltage and Load Margin For Increasing Junction Temperature HS_S Trickle Charge Pum p Load Margin and Supply Voltage at HS_S=Vsup=36V Figure 14. Typical Voltage and Load Margin For Increasing Junction Temperature HS_S 33937 100 120 Tj ( 100 120 Tj ( 140 160 180 140 160 180 Analog Integrated Circuit Device Data Freescale Semiconductor ...

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... When the charge pump is required, this pin should be connected to a polarity protected supply. This input should never be connected to a supply greater than 40 V. Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DESCRIPTIONS INTRODUCTION Because there are so many methods of controlling three phase systems, the IC enforces few constraints on driving the FETs ...

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... Low Side FET for phase C. PHASE C LOW SIDE GATE (PC_LS_G) This is the gate drive for the phase C Low Side output FET. It provides high current through a low impedance to turn on Analog Integrated Circuit Device Data Freescale Semiconductor 28 for ...

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... This is the gate drive for the phase B High Side output FET. This pin provides the gate bias to turn the external FET Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DESCRIPTIONS on or off. The gate voltage is limited to about 15 V above the FET source voltage. A low-impedance drive is used, ensuring transient currents do not overcome an off-state driver and allow pulses of current to flow in the external FETs ...

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... This pad may be connected electrically to the substrate of the device.The device will perform as specified with the Exposed Pad un-terminated (floating). However recommended that the Exposed Pad be terminated to pin 29 (VSS) and the system ground. Analog Integrated Circuit Device Data Freescale Semiconductor ...

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... The SPI registers and functionality is described completely in the LOGIC COMMANDS AND REGISTERS section of this document. SPI functionality includes the following: • Programming of deadtime delay —This delay is adjustable in approximately 50 ns steps from Analog Integrated Circuit Device Data Freescale Semiconductor Trickle Charge Pump VLS Regulator Under-voltage De-sat Phase Over-current Logic & ...

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... Px_BOOT could cause the same effect. Since this characteristic is intrinsic to the bootstrap diode integrated on the device, a valid solution to prevent an undesired reset during initialization would be to use external diodes between VLS and the Px_BOOT pin. Analog Integrated Circuit Device Data Freescale Semiconductor ...

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... The Low Side FETs must not inject detrimental substrate currents in this condition. The occurrence of these cases depends on the polarity of the load current during switching. Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL INTERNAL BLOCK DESCRIPTION 33927 Figures 11 VLS ...

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... FET Shorted Px_HS_S Phase x Output Low -Side LS Driver Control R Px_LS_G R Phase Return Px_LS_S To Current R Sense Sense Amplif. VLS_CAP Deadtime t BLANK Phase x Output Voltage Shorted to V SUP 0.5V SUP Correct Phase x Output Voltage -V D Fault Correct Analog Integrated Circuit Device Data Freescale Semiconductor ...

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... Figure 22), the regulation path Analog Integrated Circuit Device Data Freescale Semiconductor for VLS includes the charge pump and a linear regulator. The regulation set point for the linear regulator is nominally at 15. long as VLS output voltage (VLS than the VLS analog regulator threshold (VLS V , the charge pump is not active ...

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... If there is an alternate means of pre-charging the bootstrap capacitor, i.e. an external resistor from Px_HS_S to GND, then a very brief pulse of 100 ns is sufficient to reset the logic 5 0.47 µF) SUP PWR Characteristic (55) (55) Value Low (<1.0 V) High (>2.0 V) Analog Integrated Circuit Device Data Freescale Semiconductor ...

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... Thus, when an interrupt occurs, the host can query the IC by sending a NULL command; the return word contains flags Analog Integrated Circuit Device Data Freescale Semiconductor LOGIC COMMANDS AND REGISTERS in an SPI word can be considered to be the Command with the trailing five bits being the data. ...

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... From Clint Command Table 11. MASK1 Register SPI Data Bits 7 6 Write 0 0 Reset 33937 Figure 20 illustrates how interrupts are enabled and Status Register From MASKx:N Register Fault S Latch R Figure 20. Interrupt Handling net N INT net Analog Integrated Circuit Device Data Freescale Semiconductor ...

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... Disable: Desaturation /Phase Error channel shutdown is disabled, but interrupts are still possible if unmasked. Sending a MODE command and setting the Mode Lock simultaneously are allowed. This sets the requested mode and locks out any further changes. Analog Integrated Circuit Device Data Freescale Semiconductor Description 5 4 ...

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... If there are any transitions SCLK while the Deadtime CS pulse is low, a Framing Error will be generated, however, the CS pulse will be used to calibrate the deadtime Deadtime Calibration Pulse Deadtime Calibration Pulse DEADTIME Deadtime Command Command Figure 21. Deadtime Calibration ZERO/ CALIBRATE Analog Integrated Circuit Device Data Freescale Semiconductor ...

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... Bit 7 –is set upon exiting RST . It can be used to test the interrupt mechanism or to flag for a condition where the IC gets reset without the host being otherwise aware. This flag can generate an interrupt if the appropriate mask bit is set. Analog Integrated Circuit Device Data Freescale Semiconductor Other commands return a general status word in the Status Register 0. ...

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... Zero Calibration Deadtime Deadtime Overflow Calibration Set Mask1:1 Mask1:0 Mask0 Dead5 Dead4 Dead3 FULLON Lock Mode Bit Mask0:2 Mask0:1 Mask0 Dead2 Dead1 Dead0 Analog Integrated Circuit Device Data Freescale Semiconductor ...

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... Send CLINT1 command to clear processed faults 4:7. Note, the return SR0 register from this command is actually read in the main routine. 5. Re-enable interrupts from the 33937 Analog Integrated Circuit Device Data Freescale Semiconductor current will be low because it will only be leakage and the small hold off bias SYS FUNCTIONAL DEVICE OPERATION ...

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... All external FETs turned off across R • Fault bit set in Status Register SENSE • Low Side Phase Error • INT pin set high • Directly sensed by ADC as voltage across R SENSE Analog Integrated Circuit Device Data 33937 Protective Action Freescale Semiconductor ...

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... SO 3 PHASE_x OC_OUT I-sense GND Over-Cur. Comp. AMP_OUT OC_TH + - To ADC Figure 22. Typical Application Diagram Using Charge Pump (+12 V Battery System) Analog Integrated Circuit Device Data Freescale Semiconductor TYPICAL APPLICATIONS D2 C2 VPWR VPWR VSUP Trickle Hold Charge -Off 5V Pump Circuit Reg. VLS VDD Reg ...

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... Low Phase VSUP -Side Comp. Driver I-sense Amp. AMP_OUT AMP_P VLS_CAP AMP_N Other Two Phases C6 VLS C3 VDD C4 Px_BOOT x_Boot R g_HS Px_HS_G (Optional) Phase x Output To Motor Px_HS_S g_LS Px_LS_G (Optional) Phase Px_LS_S Return R1 R Sense Analog Integrated Circuit Device Data Freescale Semiconductor ...

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... Switching Single Phase Below approximately 17 V the charge pump is actively regulating V pump losses. Above this voltage the charge pump oscillator shuts down and PWR Analog Integrated Circuit Device Data Freescale Semiconductor Supply Voltage (V) . The increased power dissipation is due to the charge PWR ...

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... Switching Single Phase • No connections to PUMP or VPUMP • VPWR connected to V SYS If VPWR is supplied by a separate pre-regulator, the power dissipation profile will be nearly flat at the value of the pre-regulator voltage for all V voltages. SYS 33937 Supply Voltage ( Analog Integrated Circuit Device Data Freescale Semiconductor ...

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... For the most current package revision, visit www.freescale.com and perform a keyword search using the “98A” listed below. Analog Integrated Circuit Device Data Freescale Semiconductor PACKAGING PACKAGING DIMENSION EK SUFFIX (PB-FREE) 54-PIN 98ASA99334D ISSUE C PACKAGING PACKAGING DIMENSION 33937 45 ...

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... PACKAGING PACKAGING DIMENSION (CONTINUED) 33937 46 PACKAGING DIMENSION (CONTINUED) EK SUFFIX (PB-FREE) 54-PIN 98ASA99334D ISSUE C Analog Integrated Circuit Device Data Freescale Semiconductor ...

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... Changed part number from PCZ33937A to MCZ33937A on page 1. Added Device Variation table 9/2009 6.0 on page 2. Analog Integrated Circuit Device Data Freescale Semiconductor REVISION HISTORY VLS Regulator Outputs (VLS, VLS_CAP) Charge Device Model - CDM No output loads on Gate Drive Pins, No PWM, Outputs initialized ...

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... Freescale Semiconductor was negligent regarding the design or manufacture of the part. Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc ...