A6833SEPTR-T | |
|---|---|
| Manufacturer Part Number | A6833SEPTR-T |
| Description | IC SINK DVR 32BIT LATCH 44-PLCC |
| Manufacturer | Allegro Microsystems Inc |
| Type | Low Side |
| A6833SEPTR-T datasheets |
|
Availability: By request
International delivery:
Warranty: 60 days
×
- We provide standard 60-days warranty for all parts. If warranty differs we always mention it beforehand. In case of return we cover shipping costs.
- If you still have any questions - please contact us
×
Shipping terms
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Payment terms
- For new client payment term is payment in advance. At this moment we accept 3 payment methods: wire transfer, PayPal and Western Union. Credit card payment is under constrution and will be introduced soon. Escrow service is acceptable. Net terms for regular customers is not a problem. Working with us is totally safe for you.
- If you still have any questions - please contact us
Specifications of A6833SEPTR-T | |||
|---|---|---|---|
| Input Type | Serial | Number Of Outputs | 32 |
| Current - Peak Output | 125mA | Voltage - Supply | 3 V ~ 5.5 V |
| Operating Temperature | -20°C ~ 85°C | Mounting Type | Surface Mount |
| Package / Case | 44-LCC (J-Lead) | Supply Voltage Min | 3.3V |
| Supply Voltage Max | 5V | No. Of Outputs | 32 |
| Output Voltage | 30V | Output Current | 125mA |
| Driver Case Style | LCC | Peak Reflow Compatible (260 C) | Yes |
| Device Type | Sink | Lead Free Status / RoHS Status | Lead free / RoHS Compliant |
| Current - Output / Channel | - | On-state Resistance | - |
| Other names | 620-1311-2 A6833SEPTR-T | ||
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A6833
ELECTRICAL CHARACTERISTICS
Characteristic
Symbol
Output Leakage Current
Collector–Emitter Saturation
V
CE(SAT)
Voltage
V
Input Voltage
V
Input Current
V
Serial Data Output Voltage
V
Maximum Clock Frequency
2
I
Logic Supply Current
I
t
dis(BQ)
Output Enable-to-Output Delay
t
en(BQ)
t
p(STH-QL)
Strobe-to-Output Delay
t
p(STH-QH)
Output Fall Time
Output Rise Time
Clock-to-Serial Data Out Delay
t
p(CH-SQX)
1
Positive (negative) current is defined as conventional current going into (coming out of) the specified device pin.
2
Operation at a clock frequency greater than the specified minimum value is possible but not warran
Truth Table
Serial
Shift Register Contents
Data
Clock
Input Input I
I
I
...
I
1
2
3
N-1
H
H
R
R
...
R
1
2
L
L
R
R
...
R
1
2
X
R
R
R
...
R
1
2
3
X
X
X
...
X
P
P
P
...
P
1
2
3
N-1
L = Low Logic Level
H = High Logic Level
X = Irrelevant
DABiC-5 32-Bit Serial-Input Latched Sink Drivers
1
Unless otherwise noted: T
= 25°C, logic supply operating voltage V
A
Test Conditions
I
V
= 30 V
CEX
OUT
I
= 50 mA
OUT
I
= 100 mA
OUT
IN(1)
IN(0)
I
V
= V
IN(1)
IN
DD
I
V
= 0 V
IN(0)
IN
I
= –200 μA
OUT(1)
OUT
I
= 200 μA
OUT(0)
OUT
f
c
One output on, I
= 100 mA
DD(1)
OUT
All outputs off
DD(0)
V
= 50 V, R1 = 500 Ω, C1 ≤ 30 pF
CC
V
= 50 V, R1 = 500 Ω, C1 ≤ 30 pF
CC
V
= 50 V, R1 = 500 Ω, C1 ≤ 30 pF
CC
V
= 50 V, R1 = 500 Ω, C1 ≤ 30 pF
CC
t
V
= 50 V, R1 = 500 Ω, C1 ≤ 30 pF
f
CC
t
V
= 50 V, R1 = 500 Ω, C1 ≤ 30 pF
r
CC
I
= ±200 μA
OUT
Serial
Latch Contents
Data
Strobe
I
Output
Input
I
I
I
N
1
2
3
R
R
N-2
N-1
N-1
R
R
N-2
N-1
N-1
R
R
N-1
N
N
X
X
L
R
R
R
1
2
3
P
P
H
P
P
P
N
N
1
2
3
X
X
X
P = Present State
R = Previous State
dd
V
= 3.3 V
V
= 5 V
dd
dd
Min.
Typ.
Max. Min.
Typ.
Max.
–
–
10
–
–
–
–
0.7
–
–
–
–
1.0
–
–
2.2
–
–
3.3
–
–
–
1.1
–
–
–
< 0.01
1.0
–
< 0.01
–
< –0.01
–1.0
–
< –0.01
2.8
3.05
–
4.5
4.75
–
0.15
0.3
–
0.15
10
–
–
10
–
–
–
2.0
–
–
–
–
100
–
–
–
–
1.0
–
–
–
–
1.0
–
–
–
–
1.0
–
–
–
–
1.0
–
–
–
–
500
–
–
–
–
500
–
–
–
50
–
–
50
teed.
Output
Output Contents
Enable
...
I
I
Input
I
I
I
... I
N-1
N
1
2
3
...
R
R
N-1
N
...
P
P
H
P
P
P
... P
N-1
N
1
2
3
...
X
X
L
H H H ... H
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
= 3.0 V to 5.5 V
Units
10
μA
0.7
V
1.0
V
–
V
1.7
V
1.0
μA
–1.0
μA
–
V
0.3
V
–
MHz
2.0
mA
100
μA
1.0
μs
1.0
μs
1.0
μs
1.0
μs
500
ns
500
ns
–
ns
I
N-1
N
P
N-1
N
H
3
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