A6833SEPTR-T | |
|---|---|
| Manufacturer Part Number | A6833SEPTR-T |
| Description | IC SINK DVR 32BIT LATCH 44-PLCC |
| Manufacturer | Allegro Microsystems Inc |
| Type | Low Side |
| A6833SEPTR-T datasheets |
|
Availability: By request
International delivery:
Warranty: 60 days
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- We provide standard 60-days warranty for all parts. If warranty differs we always mention it beforehand. In case of return we cover shipping costs.
- If you still have any questions - please contact us
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Specifications of A6833SEPTR-T | |||
|---|---|---|---|
| Input Type | Serial | Number Of Outputs | 32 |
| Current - Peak Output | 125mA | Voltage - Supply | 3 V ~ 5.5 V |
| Operating Temperature | -20°C ~ 85°C | Mounting Type | Surface Mount |
| Package / Case | 44-LCC (J-Lead) | Supply Voltage Min | 3.3V |
| Supply Voltage Max | 5V | No. Of Outputs | 32 |
| Output Voltage | 30V | Output Current | 125mA |
| Driver Case Style | LCC | Peak Reflow Compatible (260 C) | Yes |
| Device Type | Sink | Lead Free Status / RoHS Status | Lead free / RoHS Compliant |
| Current - Output / Channel | - | On-state Resistance | - |
| Other names | 620-1311-2 A6833SEPTR-T | ||
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A6833
Timing Requirements and Specifications
C LOC K
S E R IAL
DAT A IN
S E R IAL
DAT A OUT
S T R OB E
OUT P UT E NAB LE
OUT
OUT P UT E NAB LE
OUT
Key
A
Data Active Time Before Clock Pulse (Data Set-Up Time)
B
Data Active Time After Clock Pulse (Data Hold Time)
C
Clock Pulse Width
D
Time Between Clock Activation and Strobe
E
Strobe Pulse Width
NOTE: Timing is representative of a 10 MHz clock. Higher speeds
may be attainable; operation at high temperatures will reduce the
specified maximum clock frequency.
S
erial Data present at the input is transferred to the shift register on
the logical 0 to logical 1 transition of the CLOCK input pulse. On
succeeding CLOCK pulses, the registers shift data information towards
the SERIAL DATA OUTPUT. The SERIAL DATA must appear at the
input prior to the rising edge of the CLOCK input waveform.
Information present at any register is transferred to the respective
latch when the STROBE is high (serial-to-parallel conversion). The
DABiC-5 32-Bit Serial-Input Latched Sink Drivers
(Logic Levels are V
and Ground)
DD
C
50%
A
B
DAT A
50%
t
p(C H-S QX)
50%
D
E
50%
HIG H = ALL OUT P UT S E NAB LE D
t
p(S T H-QL)
N
LOW = ALL OUT P UT S B LANK E D (DIS AB LE D)
50%
t
dis (B Q)
N
Description
latches will continue to accept new data as long as the STROBE is
held high. Applications where the latches are bypassed (STROBE
tied high) will require that the OUTPUT ENABLE input be low
during serial data entry.
When the OUTPUT ENABLE input is low, the output sink drivers
are disabled (OFF). The information stored in the latches is not
affected by the OUTPUT ENABLE input. With the OUTPUT
ENABLE input high, the outputs are controlled by the state of their
respective latches.
DAT A
t
p(S TH-QH)
90%
DAT A
10%
t
en(B Q)
t
t
r
f
90%
50%
DAT A
10%
Symbol
Time (ns)
t
25
su(D)
t
25
h(D)
t
50
w(CH)
t
100
su(C)
t
50
w(STH)
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
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