FEATURES
D
Industry-Standard Pin-Out
D
Enable Functions for Each Driver
D
High Current Drive Capability of ±4 A
D
Unique BiPolar and CMOS True Drive Output
Stage Provides High Current at MOSFET
Miller Thresholds
D
TTL/CMOS Compatible Inputs Independent of
Supply Voltage
D
20-ns Typical Rise and 15-ns Typical Fall
Times with 1.8-nF Load
D
Typical Propagation Delay Times of 25 ns with
Input Falling and 35 ns with Input Rising
D
4-V to 15-V Supply Voltage
D
Dual Outputs Can Be Paralleled for Higher
Drive Current
D
Available in Thermally Enhanced MSOP
Package with 4.7°C/W θjc
TM
PowerPAD
D
Rated From –40°C to 105°C
APPLICATIONS
D
Switch Mode Power Supplies
D
DC/DC Converters
D
Motor Controllers
D
Line Drivers
D
Class D Switching Amplifiers
PowerPADt is a trademark of Texas Instruments Incorporated.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
SLUS545B − NOVEMBER 2002 − REVISED NOVEMBER 2004
DESCRIPTION
The UCC27423/4/5 family of high-speed dual MOSFET
drivers can deliver large peak currents into capacitive
loads.Three standard logic options are offered –
dual-inverting, dual-noninverting and one-inverting and
one-noninverting driver. The thermally enhanced 8-pin
TM
PowerPAD
MSOP package (DGN) drastically lowers
the thermal resistance to improve long-term reliability.
It is also offered in the standard SOIC-8 (D) or PDIP-8
(P) packages.
Using a design that inherently minimizes shoot-through
current, these drivers deliver 4-A of current where it is
needed most at the Miller plateau region during the
MOSFET switching transition. A unique BiPolar and
MOSFET hybrid output stage in parallel also allows
efficient current sourcing and sinking at low supply
voltages.
The UCC27423/4/5 provides enable (ENBL) functions
to have better control of the operation of the driver
applications. ENBA and ENBB are implemented on pins
1 and 8 which were previously left unused in the industry
standard pin-out. They are internally pulled up to Vdd for
active high logic and can be left open for standard
operation.
BLOCK DIAGRAM
ENBA
1
INVERTING
INA
2
NON−INVERTING
INVERTING
GND
3
INB
4
NON−INVERTING
Copyright 2003, Texas Instruments Incorporated
www.ti.com
8
ENBB
7
OUTA
VDD
6 VDD
5
OUTB
UDG−01063
1