ISL6580CR Intersil, ISL6580CR Datasheet
ISL6580CR
Specifications of ISL6580CR
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ISL6580CR Summary of contents
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... ISL6590 are available. For more information, see the ISL6590 datasheet. Ordering Information TEMP. RANGE o PART NUMBER ( C) PACKAGE ISL6580CR 8x8 QFN L56.8x8C ISL6580CR QFN Tape & Reel ISL6580/90EVAL1 Evaluation Board ISL6580/90EVAL2 Evaluation Board ISL6580/90EVAL3 Evaluation Board Pinout ISL6580 (QFN) TOP VIEW SDATA 1 PWM 2 ...
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Block Diagram Typical Power Stage Schematic 2 ISL6580 ...
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Typical Application 3.3 V 1.8 V VDD_IO VDD_CORE ERR SOC VID[0:5] SCLK SDATA PWRGD SYSCLK OUTEN PWM IDIG NDRIVE ARX ATX ISL6590 ATRH ATRL OSC_IN OSC_OUT PWM IDIG NDRIVE TEST1 TEST2 TEST3 TEST4 MDO MDI MCS MCLK PWM IDIG NDRIVE ...
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... Functional Pin Description PIN # NAME I/O TYPE 1 SDATA I/O 3.3V CMOS Digital I/O; serial data line that carries configuration and monitoring information to and from the Intersil 2 PWM I 3.3V CMOS Digital input; pulse width modulation input to the high side driver. 3 NDRIVE I 3.3V CMOS Digital input; multifunction pin used for assigning device ID at startup. During operation, provides ...
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... LV ANALOG Low voltage analog input; positive input for the remote sense used to differentially sense the regulated 55 VDD I VDD 56 SCLK I 3.3V CMOS Digital input; typically 16.67MHz clock supplied by the Intersil ISL6590 digital controller for the PADDLE VCC I VCC Side Bar VSW O HV ANALOG Drain of high side PFET. When the PWM signal is high, VCC is switched to VSW ...
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Absolute Maximum Ratings ...
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Electrical Specifications V = 3.3VDC 25°C Unless Otherwise Specified (Continued) A PARAMETER LOGIC SIGNAL EXPECTED RANGES (PWM, SCLK, SDATA, SOC, CLK, NDRIVE) HIGH voltage Logic Level HIGH Voltage Range LOW voltage Logic Level LOW Voltage Range ...
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Electrical Specifications V = 3.3VDC 25°C Unless Otherwise Specified (Continued) A PARAMETER (Output = I = 7-bit serial signal, first bit = START bit, 6 bit current word length (MSB first), 66MHz clock frequency) DIG CURRENT ...
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Electrical Specifications V = 3.3VDC 25°C Unless Otherwise Specified (Continued) A PARAMETER ATRH (ACTIVE TRANSIENT RESPONSE HIGH) Step ATRH Step Range ATRH adjustment Range Default Address Register Default ATRL (ACTIVE TRANSIENT RESPONSE LOW) Step ATRL Step ...
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To understand the reduction of ripple current amplitude in the multi-phase circuit, examine the equation representing an individual channel’s peak-to-peak inductor current – IN OUT OUT I = ----------------------------------------------------- - ...
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Voltage Identification Codes (VID) V (V) VID4 VID3 VID2 VID1 OUT 0.8375 0.8500 0.8625 0.8750 0.8875 0.9000 0.9125 0.9250 ...
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... This gives the designer complete flexibility within the specified "max" and "min" limits. Current Sensing Current sensing is a key feature in the Intersil Digital Architecture. Precision current sensing is required to maintain accurate load lines, good current sense balancing between phases, thermal balancing, overload current, and peak current limit protection ...
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... The master oscillator frequency inside the Intersil Digital Architecture is 133.33MHz. Figure 9 shows the voltage drop across the sense resistor, the voltage at the switch node, the inductor current, and the digital voltage signal ...
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Above the resonant frequency of the output LC filter (10kHz in this case) the gain falls at a rate of 40dB/decade and the phase shift approaches –180 degrees frequency above the F = 1/(2ðC*ESR) = 500kHz in this ...
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FIGURE 16. DESIGN PARAMETER INPUT WINDOW FIGURE 17. SMALL SIGNAL DESIGN WINDOW 15 ISL6580 FIGURE 18. BODE PLOT F = Frequency of first zero Frequency of second zero Gain * frequency of first pole ...
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Compensation Methodology Due to the user interface software interface very easy to change the frequency compensation and see the resulting performance on a scope or network analyzer. Transient response is viewed by applying a transient load and monitoring ...
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FIGURE 22. ILLUSTRATION OF ATR AND NON-ATR PHASE AND TOTAL CURRENT ATRL threshold ATRL threshold VID VID V V out out ATRH threshold ATRH threshold ...
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ATRL ATRL ATRL ATRH ATRH ATRH NFET NFET NFET NFET NFET NFET i+1 i+1 i+1 PFET PFET PFET PFET PFET PFET i+1 i+1 i+1 NDRIVE NDRIVE NDRIVE NDRIVE NDRIVE NDRIVE i+1 ...
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FIGURE 26. BLOCK DIAGRAM OF PEAK CURRENT LIMITING The second way of responding to a Current Over Load is performed in the ISL6590 controller. If the sum of the average currents in all phases exceeds the Over Current Limit for ...
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OUT_EN or power to the ISL6590 is cycled. The threshold has hysteresis to eliminate oscillation. When V is low (below 7V), a bit in the status register is set CC high rises from a ...
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... MOSFET Selection In the Intersil Digital Multiphase Architecture, a critical component selection is the low side MOSFET. The power dissipation from the low and high side MOSFET is dominated by different factors. Because of the longer duty ...
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FIGURE 34. POWER DISSIPATION FOR STATIC AND DYNAMIC OPERATION The key characteristic for the low side MOSFET is the DC Rdson resistance important to get a very low Rdson value for the low side FET. For the high ...
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The turn off of the MOSFET is fundamentally the same as the turn on in reverse order (Figure 36). V level required to maintain the drain current (beginning of t4). At that point, V begins to rise at a rate ...
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The larger the die size, the higher the part costs but more effective heat flux occurs. A smaller die size can be used with a larger heat sink ...
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High Side FET. Figure 40 shows the waveform at the switch node with and without a Schottky diode ttky Dio ttk y Dio ...
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This provides a predicted average current per power stage (Figure 42). If any individual power stage reaches this over current protection level, the VRM shuts down and reports an over current fault condition. This protection feature can be disabled ...
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ESR and the ESL of the output capacitor can be substantial, as expressed below ESL ESR in in out out where V is the output ...
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DRIVE Maximum Recommended LS FET Gate Capacitance 20.0 18.0 16.0 14.0 12.0 10.0 8.0 6.0 4.0 2.0 0.0 200 400 600 Frequency [KHz] FIGURE 45. MAXIMUM GATE ...
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... User Interface Software The configuration of the ISL6590 controller and the ISL6580 power stages can be adjusted using Primarion ( ) PowerCode tm user interface software (provided by Intersil Pull Down Menus Click on Text for Descriptions 29 ISL6580 and our partner Primarion). Below are screen shots showing data entry points, pull down menus and buttons for help and a tutorial. the user interface allows the designer to adjust the ® ...
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... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use ...
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... The pin #1 identifier may be ei- ther a mold or mark feature. which provide improved electrical and thermal performance. tern Design efforts, see Intersil Technical Brief TB389. MAX NOTES 0. ...