ISL6580CR Intersil, ISL6580CR Datasheet - Page 25

• Manufacturer Part Number: ISL6580CR
• Description: IC DRIVER HIGH SIDE FET 56-QFN
• Manufacturer: Intersil
• Type: High Side/Low Side Driverr

Specifications of ISL6580CR

• Input Type: Non-Inverting
• Number Of Outputs: 12
• On-state Resistance: 20 mOhm
• Current - Output / Channel: 25A
• Current - Peak Output: 35A
• Voltage - Supply: 5 V ~ 12 V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 56-VQFN
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

of the High Side FET. Figure 40 shows the waveform at the
switch node with and without a Schottky diode.
Note that the Schottky diode provides a parallel path to the
body diode of the NFET for current flow. It is best to place
the Schottky diode as close as possible to the switch node of
the High Side FET on one pin and to the ground return of the
power supply decoupling capacitors on the other pin (as
shown in Figure 41). This way during clamping the
inductance of the Schottky diode is in parallel with the
inductances of interconnects as well as the low side NFET
therefore minimizing the overall inductance.
Schottky Selection
The most important characteristic of a Schottky diode
selected for clamping of the negative fly-back voltage is its
inductance. Axial leaded diodes typically exhibit larger
inductances. Leadless packages have low inductances in
the 2-5nH range. Physically smaller diodes are also
preferable because of their potentially lower inductance in
addition to printed circuit board space concerns.
The power dissipation in the Schottky diode is small and
limited to the non-overlap time, when the HS PFET is turned
off and before the LS NFET is turned on. Even during this
period, the body diode of the LS NFET starts conducting
shortly after the HS PFET is turned off and will share in
conducting the current. It is still necessary to ensure that a
E S R
E S R
E S L
E S L
V c c
V c c
FIGURE 40. EFFECT OF ADDING TWO SCHOTTKY DIODES
FIGURE 41. PROPER SCHOTTKY PLACEMENT PARALLELS
Brea kd o w n C la mp ing a t V ds=23 .5
No Sc h o ttky Dio d es
L
L
i1
i1
L
L
ON THE VDS OF THE HIGH SIDE SWITCH
LOW SIDE SWITCH AND ROUTING PARASITIC
EFFECTS
i4
i4
R
R
L
L
R
R
i 1
i 1
R
R
S
S
S
S
i 4
i 4
25
N o Bre a kdo w n, V ds- ma x = 19 .5
C
C
C
C
C
C
C
C
C
C
C
C
C
C
g s
g s
g s
g s
g d
g d
g d
g d
g s
g s
g s
g d
g d
g d
L
L
L
R
R
R
R
R
L
L
R
R
L
L
L
L
L
R
R
R
P
P
P
N
N
N
P
P
P
i 2
i 2
i2
i2
i 3
i 3
i3
i3
N
N
N
T w o Sc ho ttk y Dio d e s
C
C
C
C
C
C
C
d s
d s
d s
d s
d s
d s
d s
I
I
I
L
L
L
ISL6580
Schottky diode is selected that can handle the peak current
for a short period during each switching cycle.
Selection of R
When selecting the resistor value for R
characteristics have to be considered. They include:
An easy to use reference equation for calculating an
appropriate resistor when considering these values is:
This equation takes into account the resolution of the A/D
converter vs. the slew rate of the current divider between
R
For peak current limit, rather then relying on peak current
sampling, the power stage taps the I
connects directly to a comparator. The comparator turns off
the highside MOSFET if the peak current through it reaches
its limit real time at any point. The MOSFET is shut down
until the next clock cycle. The the user interface software can
program the voltage trip level (V
resistor (R
occurs (Equation 15).
If 1V were selected, the peak current limit of (I
Overload protection restricts the total average output current
of the power supply. The average current is predicted by
taking peak current samples each clock cycle. With good
current balancing, this can be translated to total current
output. To predict the average current for each power stage
with a peak current sample, an offset down must be
assumed. This current offset (Ios) is calculated from the
output inductance value, input voltage, output voltage, sense
resistor value, and number of phases in the system. When
I
SENSE
I
I
I
1. Size of Csample (6.2pF). Internal to the ISL6590.
2. # of steps (Steps = 64)
3. Ratio (M = 9,900) of transistors used for current mirror
4. Reference Voltage (V
5. Input Voltage (V
6. Output Voltage (V
7. Output Inductance (Lout)
trip
SENSE
trip
trip
and main current path in the high side MOSFET.
:
:
=
=
=
25.255A
------------------- - M
R
peak current sample is taken, Ios is subtracted from
------------------ - 9900
392 Ω
and Csample/Cesd.
V
sense
1V
SENSE
trip
⋅
⋅
⋅
SENSE
) where a peak current limit trip (I
IN
OUT
)
REF
)
= 1.25V)
trip
) across the sense
SENSE
SENSE
line and
trip
, several
) would be:
trip
(EQ. 15)
(EQ. 16)
(EQ. 14)
)