IRMCK341TR International Rectifier, IRMCK341TR Datasheet
IRMCK341TR
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IRMCK341TR Summary of contents
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Sensorless Motor Control IC for Appliances Features TM MCE (Motion Control Engine) - Hardware based computation engine for high efficiency sinusoidal sensorless control of permanent magnet AC motor Supports both interior and surface permanent magnet motors Built-in hardware peripheral for ...
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... SPI Read AC Timing...................................................................................................24 7.9 UART AC Timing...............................................................................................................25 7.10 CAPTURE Input AC Timing ...........................................................................................26 7.11 JTAG AC Timing ............................................................................................................27 7.12 OTP Programming Timing .............................................................................................28 8 I/O Structure.............................................................................................................................29 9 Pin List .....................................................................................................................................32 10 Package Dimensions ............................................................................................................35 11 Part Marking Information ......................................................................................................36 12 Order Information .................................................................................................................36 www.irf.com TABLE OF CONTENTS 2 IRMCK341 © 2007 International Rectifier ...
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... Figure 20 RESET, GATEKILL I/O ..................................................................................................29 Figure 21 Analog input ...................................................................................................................30 Figure 22 Analog operational amplifier output and AREF I/O structure.......................................30 Figure 23 VPP programming pin.................................................................................................30 Figure 24 VSS and AVSS pin structure..........................................................................................31 Figure 25 VDD1 and VDDCAP pin structure ..................................................................................31 Figure 26 XTAL0/XTAL1 pins structure .......................................................................................31 www.irf.com TABLE OF FIGURES 3 IRMCK341 © 2007 International Rectifier ...
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... Table 12. GATEKILL to SVPWM AC Timing ...............................................................................21 Table 13. Interrupt AC Timing......................................................................................................21 2 Table 14 Timing ..............................................................................................................22 Table 15. SPI Write AC Timing ....................................................................................................23 Table 16. SPI Read AC Timing....................................................................................................24 Table 17. UART AC Timing .........................................................................................................25 Table 18. CAPTURE AC Timing ..................................................................................................26 Table 19. JTAG AC Timing ..........................................................................................................27 Table 20. OTP Programming Timing ...........................................................................................28 Table 21. Pin List .........................................................................................................................34 www.irf.com TABLE OF TABLES 4 IRMCK341 © 2007 International Rectifier ...
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... Overview IRMCK341 is a new International Rectifier integrated circuit device primarily designed as a one- chip solution for complete inverter controlled appliance motor control applications. Unlike a traditional microcontroller or DSP, the IRMCK341 provides a built-in closed loop sensorless control algorithm using the unique Motion Control Engine (MCE ...
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... To IGBT Low Loss gate drive SVPWM CGATEKILL Single Shunt 3 shunt Current resistor Sensing Motion Control Modules AIN0 DC bus volt sensing A/D MUX S/H AIN1 & AIN2 OP Amp Analog AIN3 inputs AIN4 AIN5 AIN6 Motion Control Sequencer © 2007 International Rectifier ...
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... Up to three channels of analog output (8-bit PWM) o UART C/SPI port o 64K byte program OTP o 2K byte data RAM. Note 1: Total size of RAM is 8K byte including MCE program, MCE data, and 8051 data. Different sizes can be allocated depending on applications. www.irf.com Note 1 Note 1 7 IRMCK341 © 2007 International Rectifier ...
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... Pinout www.irf.com Figure 3. IRMCK341 Pin Configuration 8 IRMCK341 © 2007 International Rectifier ...
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... PWMWH PWMWL GATEKILL Analog power/ AVDD (1.8V) ground AVSS CMEXT AREF IFB+ IFB- A/D Interface IFBO AIN0 AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 VDD1 (3.3V) Digital power/ VDD2 (1.8V) ground VSS PLL power/ PLLVDD (1.8V) ground PLLVSS © 2007 International Rectifier ...
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... Input/output, can be configured as 8-bit PWM output 2 with programmable carrier frequency Crystal Interface XTAL0 Input, connected to crystal XTAL1 Output, connected to crystal Reset Interface RESET Inout, system reset, needs to be pulled up to VDD1 but doesn’t require external RC time constant www.irf.com © 2007 International Rectifier 10 IRMCK341 ...
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... Input, Analog input channel 4 (0 – 1.2V), needs to be pulled down to AVSS if unused www.irf.com 2 C clock output, or SPI data 2 C Data line or SPI chip select clock output, or SPI data or OTP programming power 2 C data line or SPI chip select 0 11 IRMCK341 © 2007 International Rectifier ...
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... Must be tied to VSS, used only for factory testing. P5.1/TSM Input/output port 5.1, configured as JTAG port by default P5.2/TDO Input/output port 5.2, configured as JTAG port by default P5.3/TDI Input/output port 5.3, configured as JTAG port by default TCK Input, JTAG test clock www.irf.com © 2007 International Rectifier 12 IRMCK341 ...
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... Application Connections Typical application connection is shown in Figure 5. All components necessary to implement a complete sensorless drive control algorithm are shown connected to IRMCK341. Figure 5. Application Connection of IRMCK341 www.irf.com © 2007 International Rectifier 13 IRMCK341 ...
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... Power Consumption 1.8V 3.3V Total Power MCE Frequency (MHz) 14 IRMCK341 Max Condition 3.6 V Respect to VSS 1.98 V Respect to VSS 7.0V Respect to VSS 1.98 V Respect to AVSS 3.65 V Respect to VSS 85 ˚C 150 ˚C Max Unit 128 MHz 32 MHz 100 120 140 © 2007 International Rectifier ...
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... V 6.5V 6.75V -0 2 3.6 pF ±10 nA 8.9 mA 13.2 mA 12.4 mA 24.8 mA 17.9 mA 26.3 mA 24.6 mA 49.5 mA Table 3. Digital I/O DC Characteristics 15 IRMCK341 Max Condition 3.6 V Recommended 1.98 V Recommended 7.0V Recommended 0.8 V Recommended 3.6 V Recommended (1) - ±1 μ ( (1) © 2007 International Rectifier ...
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... Table 5. Analog I/O DC Characteristics 16 IRMCK341 Max Condition 1.92 V Recommended 0. 1.8 V PLLVDD (1) V PLLVDD 1.8 V PLLVDD PLLVDD (1) Max Condition 1.89 V Recommended 1.8 V AVDD 1.2 V Recommended 1 1.8 V AVDD (1) - Requested 20 kΩ between IFBO and IFB- ( 0.6 V OUT ( 0.6 V OUT (1) © 2007 International Rectifier ...
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... Power Supply Rejection Ratio Note: (1) Data guaranteed by design. www.irf.com Min Typ 1.53 V 1.66 V 1. Table 6. UVcc DC Characteristics Min Typ 495 mV 600 mV -0. Table 7. AREF DC Characteristics 17 IRMCK341 Max Condition 1. 3.3 V DD1 1. 3.3 V DD1 - Max Condition 700 1.8 V AVDD (1) - (1) - © 2007 International Rectifier ...
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... MHz 4 MHz 32 MHz 50 MHz F ÷ 256 - CLKIN - 200 psec - Table 8. PLL AC Characteristics R = =10 Xtal 2 C =30PF 1 C =30PF 2 Figure 7 Crystal oscillator circuit 18 IRMCK341 Max Condition (1) 60 MHz (see figure below) (1) 128 MHz (1) - (1) - (1) - (1) 500 μsec © 2007 International Rectifier ...
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... Data guaranteed by design. www.irf.com Min Typ - - - - Voltage droop t SAMPLE T HOLD Min Typ - 10 V/μsec Ω - 400 ns 19 IRMCK341 Max Condition (1) 2.05 μsec 10 μsec Voltage droop ≤ 15 LSB (see figure below) S/H Voltage Max Condition - AVDD ( ( 1 AVDD ( © 2007 International Rectifier ...
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... SYNC to PWM output dSYNC3 delay time Note: (1) AIN1 through AIN6 channels are converted once every 6 SYNC events www.irf.com t wSYNC t dSYNC1 t dSYNC2 t dSYNC3 Min Typ - Table 11. SYNC AC Characteristics 20 IRMCK341 Max Unit - SYSCLK 100 SYSCLK 200 SYSCLK (1) 2 SYSCLK © 2007 International Rectifier ...
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... Interrupt AC Timing Unless specified 25˚C. Symbol Parameter t INT0, INT1 Interrupt wINT Assertion Time t INT0, INT1 latency dINT www.irf.com Min Typ Figure 11 Interrupt AC Timing Min Typ Table 13. Interrupt AC Timing 21 IRMCK341 Max Unit - SYSCLK 100 SYSCLK Max Unit - SYSCLK 4 SYSCLK © 2007 International Rectifier ...
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... C read setup time is determined by the programmable filter time applied to I communication. www.irf.com T T I2CLK I2CLK I2WSETUP I2WHOLD I2RSETUP 2 Figure Timing Min Typ 10 0.25 0.25 0.25 0. filter time 1 2 Table 14 Timing 22 IRMCK341 t I2EN1 t I2RHOLD t I2EN2 Max Unit - 8192 SYSCLK - - T I2CLK - - T I2CLK - - T I2CLK - - T I2CLK - - SYSCLK - - SYSCLK 2 C © 2007 International Rectifier ...
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... CS high time between two CSHIGH consecutive byte transfer t CS hold time CSHOLD www.irf.com Figure 13 SPI Write AC Timing Min Typ 1 Table 15. SPI Write AC Timing 23 IRMCK341 Max Unit - SYSCLK - T SPICLK - T SPICLK 10 nsec 10 nsec - T SPICLK - T SPICLK © 2007 International Rectifier ...
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... RDHOLD t CS high time between two CSHIGH consecutive byte transfer t CS hold time CSHOLD www.irf.com Figure 14 SPI Read AC Timing Min Typ 1 Table 16. SPI Read AC Timing 24 IRMCK341 Max Unit - SYSCLK - T SPICLK - T SPICLK 10 nsec - nsec - nsec - T SPICLK - T SPICLK © 2007 International Rectifier ...
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... Each bit including start and stop bit is sampled three times at center of a bit at an interval of 1/ three sampled values do not agree, then UART noise error is generated. BAUD www.irf.com Data and Parity Bit Stop Bit T UARTFIL Figure 15 UART AC Timing Min Typ - 57600 - 1/16 Table 17. UART AC Timing 25 IRMCK341 Max Unit - bit/sec - T BAUD © 2007 International Rectifier ...
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... CAPTURE rising edge CLDELAY to capture register latch time t CAPTURE input INTDELAY interrupt latency time www.irf.com Figure 16 CAPTURE Input AC Timing Min Typ Table 18. CAPTURE AC Timing 26 IRMCK341 Max Unit - SYSCLK - SYSCLK - SYSCLK 4 SYSCLK 4 SYSCLK 4 SYSCLK © 2007 International Rectifier ...
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... JHIGH t TCK Low Period JLOW t TCK to TDO propagation CO delay time t TDI/TMS setup time JSETUP t TDI/TMS hold time JHOLD www.irf.com t JHOLD Figure 17 JTAG AC Timing Min - Table 19. JTAG AC Timing 27 IRMCK341 Typ Max Unit - 50 MHz - - nsec - - nsec - 5 nsec - - nsec - - nsec © 2007 International Rectifier ...
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OTP Programming Timing Figure 18 OTP Programming Timing Unless specified 25˚C. Symbol Parameter T VPP Setup Time VPS T VPP Hold Time VPH Rev 1.0 Min 10 15 Table 20. OTP Programming Timing Typ Max Unit - ...
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... Figure 19 All digital I/O except motor PWM output The following figure shows RESET and GATEKILL I/O structure. www.irf.com VDD1 (3.3V) 70k Low true logic 6.0V 100 6.0V VSS VDD1 (3.3V) RESET GATEKILL I/O 6.0V PIN 100 6.0V VSS Figure 20 RESET, GATEKILL I/O 29 IRMCK341 70k © 2007 International Rectifier ...
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... The following figure shows the VPP pin I/O structure www.irf.com AVDD Analog input 6.0V PIN 100 Analog Circuit 6.0V AVSS Figure 21 Analog input 1.8V Analog output 6.0V PIN Analog Circuit 6.0V AVSS VPP input PIN 100 Analog Circuit 8.0V VSS Figure 23 VPP programming pin 30 IRMCK341 © 2007 International Rectifier ...
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... The following figure shows the VDD1, VDD2, AVDD and PLLVDD pin structure Figure 25 VDD1, VDD2, AVDD and PLLVDD pin structure The following figure shows the XTAL0 and XTAL1 pins structure www.irf.com 6.0V PIN Figure 26 XTAL0/XTAL1 pins structure 31 IRMCK341 VDD1 6.0V VSS © 2007 International Rectifier ...
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... Analog input channel 1, 0-1.2V range, needs to be pulled down to AVSS if unused O Unbuffered 0.6V output. Capacitor needs to be connected. O Analog reference voltage output (0.6V) I Single shunt current sensing OP amp input (-) I Single shunt current sensing OP amp input (+) O Single shunt current sensing OP amp output 32 IRMCK341 © 2007 International Rectifier ...
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... C clock output (open drain, need pull up) or SPI data or OTP power supply for programming 2 I data (open drain, need pull up) or SPI Chip Select 0 I/O JTAG test mode select I/O JTAG test data output I/O JTAG test data input I JTAG test clock 33 IRMCK341 © 2007 International Rectifier ...
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... PLLVDD 64 PLLVSS www.irf.com Internal Pin Pull-up Type Description /Pull-down 58 kΩ pull I Test mode. Must be tied to VSS. Factory use only down I/O Reset, low true, Schmitt trigger input P 1.8V PLL power P PLL ground Table 21. Pin List 34 IRMCK341 © 2007 International Rectifier ...
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... Package Dimensions This document is the property of International Rectifier and may not be copied or distributed without expressed consent. IRMCK341 ...
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... Lead-Free Part in 64-lead QFP Moisture Sensitivity Rating – MSL3 Part number Order quantities IRMCK341TR 1500 parts on tape and reel in dry pack IRMCK341TY 1600 parts on trays (160 parts per tray) in dry pack IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, Tel: (310) 252-7105 www ...