IRMCK343TY International Rectifier, IRMCK343TY Datasheet
IRMCK343TY
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IRMCK343TY Summary of contents
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... Analog output (PWM) resolution UART baud rate (typ) Number of I/O (max) Package (lead-free) Operating temperature TM ) for sensorless control of permanent TM is seamlessly integrated into the © 2007 International Rectifier Data Sheet No. PD60336 60 MHz 128 MHz 33 MHz 11 μsec typ 16 bit signed 56K bytes 8K bytes 2 μ ...
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... SPI Read AC Timing...................................................................................................23 7.9 UART AC Timing...............................................................................................................24 7.10 CAPTURE Input AC Timing ...........................................................................................25 7.11 JTAG AC Timing ............................................................................................................26 7.12 OTP Programming Timing .............................................................................................27 8 I/O Structure.............................................................................................................................28 9 Pin List .....................................................................................................................................31 10 Package Dimensions ............................................................................................................34 11 Part Marking Information ......................................................................................................35 12 Order Information .................................................................................................................35 www.irf.com TABLE OF CONTENTS 2 IRMCK343 © 2007 International Rectifier ...
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... Figure 21 Analog input ...................................................................................................................29 Figure 22 Analog operational amplifier output and AREF I/O structure.......................................29 Figure 23 VPP programming pin.................................................................................................29 Figure 24 VSS, AVSS and PLLVSS pin structure ..........................................................................30 Figure 25 VDD1, VDD2, AVDD and PLLVDD pin structure ...........................................................30 Figure 26 XTAL0/XTAL1 pins structure .......................................................................................30 www.irf.com TABLE OF FIGURES 3 IRMCK343 © 2007 International Rectifier ...
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... Table 12. GATEKILL to SVPWM AC Timing ...............................................................................20 Table 13. Interrupt AC Timing......................................................................................................20 2 Table 14 Timing ..............................................................................................................21 Table 15. SPI Write AC Timing ....................................................................................................22 Table 16. SPI Read AC Timing....................................................................................................23 Table 17. UART AC Timing .........................................................................................................24 Table 18. CAPTURE AC Timing ..................................................................................................25 Table 19. JTAG AC Timing ..........................................................................................................26 Table 20. OTP Programming Timing ...........................................................................................27 Table 21. Pin List .........................................................................................................................33 www.irf.com TABLE OF TABLES 4 IRMCK343 © 2007 International Rectifier ...
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... Overview IRMCK343 is a new International Rectifier integrated circuit device primarily designed as a one- chip solution for complete inverter controlled appliance motor control applications. Unlike a traditional microcontroller or DSP, the IRMCK343 provides a built-in closed loop sensorless control algorithm using the unique Motion Control Engine (MCE ...
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... IRMCK343 contains the following functions for sensorless AC motor control applications: • Motion Control Engine (MCE o Proportional plus Integral block o Low pass filter o Differentiator and lag (high pass filter) o Ramp o Limit o Angle estimate (sensorless control) o Inverse Clark transformation o Vector rotator o Bit latch o Peak detect www.irf.com IRMCK343 © 2007 International Rectifier ...
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... Up to three channels of analog output (8-bit PWM) o UART C/SPI port o 64K byte program OTP o 2K byte data RAM. Note 1: Total size of RAM is 8K byte including MCE program, MCE data, and 8051 data. Different sizes can be allocated depending on applications. www.irf.com Note 1 Note 1 7 IRMCK343 © 2007 International Rectifier ...
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... P1.5 8 P1.6 9 P1.7 10 VDD2 11 VSS 12 VDD1 13 P2.0/NMI 14 P2 www.irf.com (Top View) Figure 3. IRMCK343 Pin Configuration 8 IRMCK343 48 P3.0/INT2/CS1 47 PWMUH PWMUL 46 45 PWMVH 44 PWMVL PWMWH 43 42 PWMWL GATEKILL 41 VDD1 40 39 VSS IPFC IPFC+ 36 IPFCO VACO 35 34 VAC- VAC+ 33 © 2007 International Rectifier ...
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... PFC PWM PWMWL gate signal GATEKILL Interface AREF CMEXT IPFC+ IPFC- IPFCO IFB+ IFB- A/D Interface IFBCO VAC+ VAC- VACO AIN0 AIN1 Analog power/ AVDD ground AVSS VDD1 Digital power/ VDD2 ground VSS PLL power/ PLLVDD ground PLLVSS © 2007 International Rectifier ...
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... P5.0/PFCGKILL Input, upon assertion, this negates PFCPWM signal, programmable logic sense, can be configured as discrete I/O in which case CGATEKILL negates PFCPWM www.irf.com 2 C clock output or SPI data or OTP Programming 2 C data line or SPI chip select EEPROM 10 IRMCK343 © 2007 International Rectifier ...
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... Test Interface Group TSTMOD Must be tied to VSS, used only for factory testing. P5.3/TDI Input, JTAG test data input P5.1/TMS Input, JTAG test mode select TCK Input, JTAG test clock P5.2/TDO Output, JTAG test data output www.irf.com © 2007 International Rectifier 11 IRMCK343 ...
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... Application Connections Typical application connection is shown in Figure 5. All components necessary to implement a complete sensorless drive control algorithm are shown connected to IRMCK343. Figure 5. Application Connection of IRMCK343 www.irf.com © 2007 International Rectifier 12 IRMCK343 ...
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... Table 2. System Clock Frequency Power Consumption 1.8V 3.3V Total Power MCE Frequency (MHz) 13 IRMCK343 Max Condition 3.6 V Respect to VSS 1.98 V Respect to VSS 1.98 V Respect to AVSS 3.65 V Respect to VSS 85 ˚C 150 ˚C Max Unit 128 MHz 32 MHz 100 120 140 © 2007 International Rectifier ...
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... Typ 1. PLLVSS 0.8* V PLLVDD Table 4. PLL DC Characteristics 14 IRMCK343 Max Condition 3.6 V Recommended 1.98 V Recommended 0.8 V Recommended 3.6 V Recommended (1) - ±1 μ ( (1) Max Condition 1.92 V Recommended 0. 1.8 V PLLVDD (1) V PLLVDD 1.8 V PLLVDD PLLVDD (1) © 2007 International Rectifier ...
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... Min Typ 1. ( kΩ 100 μA Table 5. Analog I/O DC Characteristics 15 IRMCK343 Max Condition 1.89 V Recommended 1.8 V AVDD 1.2 V Recommended 1 1.8 V AVDD (1) - Requested 20 kΩ between op amp output and negative input ( 0.6 V OUT ( 0.6 V OUT (1) © 2007 International Rectifier ...
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... Power Supply Rejection Ratio Note: (1) Data guaranteed by design. www.irf.com . Min Typ 1.53 V 1.66 V 1. Table 6. UVcc DC Characteristics Min Typ 495 mV 600 mV -0. Table 7. AREF DC Characteristics Max Condition 1. 3.3 V DD1 1. 3.3 V DD1 - Max Condition 700 1.8 V AVDD (1) - (1) - © 2007 International Rectifier ...
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... MHz 4 MHz 32 MHz 50 MHz F ÷ 256 - CLKIN - 200 psec - Table 8. PLL AC Characteristics R = =10 Xtal 2 C =30PF 1 C =30PF 2 Figure 7 Crystal oscillator circuit 17 IRMCK343 Max Condition (1) 60 MHz (see figure below) (1) 128 MHz (1) - (1) - (1) - (1) 500 μsec © 2007 International Rectifier ...
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... Data guaranteed by design. www.irf.com Min Typ - - - - Voltage droop t SAMPLE T HOLD Min Typ - 10 V/μsec Ω - 400 ns 18 IRMCK343 Max Condition (1) 2.05 μsec 10 μsec Voltage droop ≤ 15 LSB (see figure below) S/H Voltage Max Condition - AVDD ( ( 1 AVDD ( © 2007 International Rectifier ...
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... SYNC to PWM output dSYNC3 delay time Note: (1) AIN1 through AIN6 channels are converted once every 6 SYNC events www.irf.com t wSYNC t dSYNC1 t dSYNC2 t dSYNC3 Min Typ - Table 11. SYNC AC Characteristics 19 IRMCK343 Max Unit - SYSCLK 100 SYSCLK 200 SYSCLK (1) 2 SYSCLK © 2007 International Rectifier ...
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... Interrupt AC Timing Unless specified 25˚C. Symbol Parameter t INT0, INT1 Interrupt wINT Assertion Time t INT0, INT1 latency dINT www.irf.com Min Typ Figure 11 Interrupt AC Timing Min Typ Table 13. Interrupt AC Timing 20 IRMCK343 Max Unit - SYSCLK 100 SYSCLK Max Unit - SYSCLK 4 SYSCLK © 2007 International Rectifier ...
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... C read setup time is determined by the programmable filter time applied to I communication. www.irf.com T T I2CLK I2CLK I2WSETUP I2WHOLD I2RSETUP 2 Figure Timing Min Typ 10 0.25 0.25 0.25 0. filter time 1 2 Table 14 Timing 21 IRMCK343 t I2EN1 t I2RHOLD t I2EN2 Max Unit - 8192 SYSCLK - - T I2CLK - - T I2CLK - - T I2CLK - - T I2CLK - - SYSCLK - - SYSCLK 2 C © 2007 International Rectifier ...
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... CS high time between two CSHIGH consecutive byte transfer t CS hold time CSHOLD www.irf.com Figure 13 SPI write AC Timing Min Typ 1 Table 15. SPI Write AC Timing 22 IRMCK343 Max Unit - SYSCLK - T SPICLK - T SPICLK 10 nsec 10 nsec - T SPICLK - T SPICLK © 2007 International Rectifier ...
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... RDHOLD t CS high time between two CSHIGH consecutive byte transfer t CS hold time CSHOLD www.irf.com Figure 14 SPI read AC Timing Min Typ 1 Table 16. SPI Read AC Timing 23 IRMCK343 Max Unit - SYSCLK - T SPICLK - T SPICLK 10 nsec - nsec - nsec - T SPICLK - T SPICLK © 2007 International Rectifier ...
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... Each bit including start and stop bit is sampled three times at center of a bit at an interval of 1/ three sampled values do not agree, then UART noise error is generated. BAUD www.irf.com Data and Parity Bit Stop Bit T UARTFIL Figure 15 UART AC Timing Min Typ - 57600 - 1/16 Table 17. UART AC Timing 24 IRMCK343 Max Unit - bit/sec - T BAUD © 2007 International Rectifier ...
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... CAPTURE rising edge CLDELAY to capture register latch time t CAPTURE input INTDELAY interrupt latency time www.irf.com Figure 16 CAPTURE Input AC Timing Min Typ Table 18. CAPTURE AC Timing 25 IRMCK343 Max Unit - SYSCLK - SYSCLK - SYSCLK 4 SYSCLK 4 SYSCLK 4 SYSCLK © 2007 International Rectifier ...
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... JHIGH t TCK Low Period JLOW t TCK to TDO propagation CO delay time t TDI/TMS setup time JSETUP t TDI/TMS hold time JHOLD www.irf.com t JHOLD Figure 17 JTAG AC Timing Min - Table 19. JTAG AC Timing 26 IRMCK343 Typ Max Unit - 50 MHz - - nsec - - nsec - 5 nsec - - nsec - - nsec © 2007 International Rectifier ...
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... OTP Programming Timing Unless specified 25˚C. Symbol Parameter T VPP Setup Time VPS T VPP Hold Time VPH www.irf.com . Figure 18 OTP Programming Timing Min 10 15 Table 20. OTP Programming Timing Typ Max Unit - - nsec - - nsec © 2007 International Rectifier ...
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... Figure 19 All digital I/O and motor PWM output The following figure shows RESET and GATEKILL I/O structure. www.irf.com VDD1 (3.3V) 70k Low true logic 6.0V 100 6.0V VSS VDD1 (3.3V) RESET GATEKILL I/O 6.0V PIN 100 6.0V VSS Figure 20 RESET, GATEKILL I/O 28 IRMCK343 70k © 2007 International Rectifier ...
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... The following figure shows the VPP pin I/O structure www.irf.com AVDD Analog input 6.0V PIN 100 Analog Circuit 6.0V AVSS Figure 21 Analog input 1.8V Analog output 6.0V PIN Analog Circuit 6.0V AVSS VPP input PIN 100 Analog Circuit 8.0V VSS Figure 23 VPP programming pin 29 IRMCK343 © 2007 International Rectifier ...
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... The following figure shows the VDD1, VDD2, AVDD and PLLVDD pin structure Figure 25 VDD1, VDD2, AVDD and PLLVDD pin structure The following figure shows the XTAL0 and XTAL1 pins structure www.irf.com 6.0V PIN Figure 26 XTAL0/XTAL1 pins structure 30 IRMCK343 VDD1 6.0V VSS © 2007 International Rectifier ...
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... Analog common I Analog input channel 1, 0-1.2V range, needs to be pulled down to AVSS if unused O Unbuffered 0.6V output. Capacitor needs to be connected. O Analog reference voltage output (0.6V) I Single shunt current sensing OP amp input (-) I Single shunt current sensing OP amp input (+) 31 IRMCK343 © 2007 International Rectifier ...
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... C data (open drain, need pull up) or SPI chip select 0 I/O Discrete programmable I/O or JTAG test mode select I/O Discrete programmable I/O or JTAG test data output I/O Discrete programmable I/O or JTAG test data input I JTAG test clock 32 IRMCK343 © 2007 International Rectifier ...
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... TSTMOD 62 RESET 63 PLLVDD 64 PLLVSS www.irf.com Pin Type Description 58 kΩ pull I Test mode. Must be tied to VSS. Factory use down only I/O Reset, low true, Schmitt trigger input P 1.8V PLL power P PLL ground Table 21. Pin List 33 IRMCK343 © 2007 International Rectifier ...
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... Package Dimensions www.irf.com © 2007 International Rectifier 34 IRMCK343 ...
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... Moisture Sensitivity Rating – MSL3 Part number Order quantities IRMCK343TR 1500 parts on tape and reel in dry pack IRMCK343TY 1600 parts on trays (160 parts per tray) in dry pack www.irf.com This product has been designed and qualified for the industrial level Qualification standards can be found at IR WORLD HEADQUARTERS: 233 Kansas St ...