LTC4412IS6#TRMPBF Linear Technology, LTC4412IS6#TRMPBF Datasheet - Page 6

IC PWR PATH CNTRLR TSOT23-6

LTC4412IS6#TRMPBF

Manufacturer Part Number
LTC4412IS6#TRMPBF
Description
IC PWR PATH CNTRLR TSOT23-6
Manufacturer
Linear Technology
Series
PowerPath™r
Datasheet

Specifications of LTC4412IS6#TRMPBF

Applications
Handheld/Mobile Devices
Fet Type
P-Channel
Number Of Outputs
1
Internal Switch(s)
No
Delay Time - On
110µs
Delay Time - Off
13µs
Voltage - Supply
2.5 V ~ 28 V
Current - Supply
16µA
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
TSOT-23-6, TSOT-6
Operating Temperature (max)
85C
Operating Temperature (min)
-40C
Pin Count
6
Mounting
Surface Mount
Package Type
TSOT-23
Case Length
2.9mm
Screening Level
Industrial
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
LTC4412IS6#TRMPBFTR

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Manufacturer
Quantity
Price
Company:
Part Number:
LTC4412IS6#TRMPBF
Manufacturer:
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Quantity:
20 000
Company:
Part Number:
LTC4412IS6#TRMPBFLTC4412IS6#TRPBF
Manufacturer:
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LTC4412
OPERATIO
6
Operation can best be understood by referring to the Block
Diagram, which illustrates the internal circuit blocks along
with the few external components, and the graph that
accompanies Figure 1. The terms primary and auxiliary are
arbitrary and may be changed to suit the application.
Operation begins when either or both power sources are
applied and the CTL control pin is below the input low
voltage of 0.35V (V
present, the Power Source Selector will power the LTC4412
from the V
Analog Controller block that is proportional to the voltage
difference in the V
SENSE is lower than V
Controller will instruct the Linear Gate Driver and Voltage
Clamp block to pull down the GATE pin voltage and turn on
the external P-channel MOSFET. The dynamic pull-down
current of 50μA (I
reaches ground or the gate clamp voltage. The gate clamp
voltage is 7V (V
As the SENSE voltage pulls up to V
will regulate the GATE voltage to maintain a 20mV differ-
ence between V
MOSFET. The system is now in the forward regulation
mode and the load will be powered from the primary
supply. As the load current varies, the GATE voltage will be
controlled to maintain the 20mV difference. If the load
current exceeds the P-channel MOSFET’s ability to deliver
the current with a 20mV V
the MOSFET will behave as a fixed resistor and the forward
voltage will increase slightly. While the MOSFET is on the
STAT pin is an open circuit.
When an auxiliary supply is applied, the SENSE pin will be
pulled higher than the V
IN
pin. Amplifier A1 will deliver a current to the
IN
G(ON)
U
IN
and V
G(SNK)
and SENSE pins. While the voltage on
) below the higher of V
IL
). If only the primary supply is
SENSE
IN
IN
) stops when the GATE voltage
DS
pin through the external diode.
– 20mV (V
the GATE voltage will clamp,
which is also the V
IN
– 20mV, the LTC4412
FR
), the Analog
IN
or V
DS
SENSE
of the
.
The Power Source Selector will power the LTC4412 from
the SENSE pin. As the SENSE voltage pulls above V
20mV, the Analog Controller will instruct the Linear Gate
Driver and Voltage Clamp block to pull the GATE voltage up
to turn off the P-channel MOSFET. When the voltage on
SENSE is higher than V
Controller will instruct the Linear Gate Driver and Voltage
Clamp block to rapidly pull the GATE pin voltage to the
SENSE pin voltage. This action will quickly finish turning
off the external P-channel MOSFET if it hasn’t already
turned completely off. For a clean transistion, the reverse
turn-off threshold has hysteresis to prevent uncertainty.
The system is now in the reverse turn-off mode. Power to
the load is being delivered through the external diode and
no current is drawn from the primary supply. The external
diode provides protection in case the auxiliary supply is
below the primary supply, sinks current to ground or is
connected reverse polarity. During the reverse turn-off
mode of operation the STAT pin will sink 10μA of current
(I
wired so that the drain to source diode will momentarily
forward bias when power is first applied to V
become reverse biased when an auxiliary supply is ap-
plied.
When the CTL (control) input is asserted high, the external
MOSFET will have its gate to source voltage forced to a
small voltage V
current if connected. This feature is useful to allow control
input switching of the load between two power sources as
shown in Figure 4 or as a switchable high side driver as
shown in Figure 7. A 3.5μA internal pull- down current
(I
should become open.
S(SNK)
CTL
) on the CTL pin will insure a low level input if the pin
) if connected. Note that the external MOSFET is
G(OFF)
and the STAT pin will sink 10μA of
IN
+ 20mV (V
RTO
), the Analog
IN
and will
4412fa
IN

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