ICE1PCS01G Infineon Technologies, ICE1PCS01G Datasheet - Page 10

• Manufacturer Part Number: ICE1PCS01G
• Description: IC PFC CONTROLLER CCM DSO8
• Manufacturer: Infineon Technologies

Specifications of ICE1PCS01G

• Mode: Continuous Conduction (CCM)
• Frequency - Switching: 133kHz
• Current - Startup: 100µA
• Voltage - Supply: 10.2 V ~ 21 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: DSO-8
• Switching Frequency: 40 KHz to 320 KHz
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ICE1PCS01GNT; ICE1PCS01GXT; SP000081001

Assuming the voltage loop is working and output
voltage is kept constant, the off duty cycle D
CCM PFC system is given as
From the above equation, D
The objective of the current loop is to regulate the
average inductor current such that it is proportional to
the off duty cycle D
V
objective.
Figure 11
The PWM is performed by the intersection of a ramp
signal with the averaged inductor current at pin 5
(ICOMP). The PWM cycle starts with the Gate turn off
for a duration of T
kept discharged. The ramp is then allowed to rise after
T
ends at the intersection of the ramp signal and the
averaged current waveform. This results in the
proportional relationship between the average current
and the off duty cycle D
Figure 12 shows the timing diagrams of T
PWM waveforms.
Figure 12
Version 1.2
D
GATE
drive
OFFMIN
IN
OFF
V
V
PWM
. Figure 11 shows the scheme to achieve the
(1)
CREF
RAMP
V
=
CREF
(1)
expires. The off time of the boost transistor
------------- -
V
V
OUT
is a function of V
IN
ramp profile
Average Current Control in CCM
Ramp and PWM waveforms
250ns
OFFMIN
OFF
, and thus to the input voltage
OFF
T
(250ns typ.) and the ramp is
OFFMIN
.
ICOMP
OFF
is proportional to V
PWM cycle
ave(I
released
ramp
IN
) at ICOMP
OFFMIN
OFF
and the
t
t
for a
IN
.
10
3.6.4
The nonlinear gain block controls the amplitude of the
regulated inductor current. The input of this block is the
voltage at pin VCOMP. This block has been designed
to support the wide input voltage range (85-265VAC).
3.7
The PWM logic block prioritizes the control input
signals and generates the final logic signal to turn on
the driver stage. The speed of the logic gates in this
block, together with the width of the reset pulse T
are designed to meet a maximum duty cycle D
95% at the GATE output under 133kHz of operation.
In case of high input currents which result in Peak
Current Limitation, the GATE will be turned off
immediately and maintained in off state for the current
PWM cycle. The signal Toffmin resets (highest priority,
overriding other input signals) both the current limit
latch and the PWM on latch as illustrated in Figure 13.
Figure 13
3.8
The voltage loop is the outer loop of the cascaded
control scheme which controls the PFC output bus
voltage V
sensing voltage at VSENSE which is a resistive divider
tapping from V
OTA1 which has an internal reference of 5V. Figure 14
shows the important blocks of this voltage loop.
3.8.1
The compensation of the voltage loop is installed at the
VCOMP pin (see Figure 14). This is the output of OTA1
and the compensation must be connected at this pin to
ground. The compensation is also responsible for the
soft start function which controls an increasing AC input
current during start-up.
PWM on signal
Current Loop
Peak Current
Toffmin
250ns
PWM Logic
Voltage Loop
OUT
Nonlinear Gain Block
Voltage Loop Compensation
Limit
PWM Logic
. This loop is closed by the feedback
OUT
. The pin VSENSE is the input of
Limit Latch
Current
PWM on
S
R
Latch
S
R
Functional Description
L1
L2
Q
Q
ICE1PCS01/G
G1
CCM-PFC
06 Feb 2007
turn GATE on
HIGH =
OFFMIN
MAX
of
,