ICE1CS02G

Manufacturer Part NumberICE1CS02G
DescriptionIC PFC CTRLR AVERAGE CURR DSO16
ManufacturerInfineon Technologies
ICE1CS02G datasheet
 


Specifications of ICE1CS02G

ModeAverage CurrentFrequency - Switching65kHz
Current - Startup1.3mAVoltage - Supply11 V ~ 25 V
Operating Temperature-40°C ~ 150°CMounting TypeSurface Mount
Package / CaseDSO-16Lead Free Status / RoHS StatusLead free / RoHS Compliant
Other namesSP000444092
SP000783614
  
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The objective of the current loop is to regulate the
average inductor current such that it is proportional to
the off duty cycle D
, and thus to the input voltage
OFF
V
. Figure 14 shows the scheme to achieve the
IN
objective.
ramp profile
GATE
drive
Figure 13
Average Current Control in CCM
The PWM is performed by the intersection of a ramp
signal with the averaged inductor current at pin 1 (PFC
ICOMP). The PWM cycle starts with the Gate turn off
for a duration of T
(400ns typ.) and the ramp is
OFFMIN
kept discharged. The ramp is then allowed to rise after
T
expires. The off time of the boost transistor
OFFMIN
ends at the intersection of the ramp signal and the
averaged current waveform. This results in the
proportional relationship between the average current
and the off duty cycle D
.
OFF
Figure 15 shows the timing diagrams of T
PWM waveforms.
T
OFFMIN
400ns
(1)
V
CREF
V
RAMP
PWM
(1)
V
is a function of V
CREF
ICOMP
Figure 14
Ramp and PWM waveforms
3.4.11
Nonlinear Gain Block
The nonlinear gain block controls the amplitude of the
regulated inductor current. The input of this block is the
voltage at pin 4 (PFC VCOMP). This block has been
Version 1.0
designed to support the wide input voltage range (85-
265VAC).
3.4.12
The PWM logic block prioritizes the control input
signals and generates the final logic signal to turn on
the driver stage. The speed of the logic gates in this
ave(I
) at ICOMP
IN
block, together with the width of the reset pulse T
are designed to meet a maximum duty cycle D
95% at the GATE output under 65kHz of operation.
In case of high input currents which result in Peak
Current Limitation, the GATE will be turned off
immediately and maintained in off state for the current
PWM cycle. The signal Toffmin resets (highest priority,
overriding other input signals) both the current limit
latch and the PWM on latch as illustrated in Figure 16.
t
Peak Current
Current Loop
PWM on signal
Figure 15
and the
OFFMIN
3.4.13
The voltage loop is the outer loop of the cascaded
control scheme which controls the PFC output bus
voltage V
PWM cycle
sensing voltage at VSENSE which is a resistive divider
tapping from V
OTA1 which has an internal reference of 3V. Figure 17
shows the important blocks of this voltage loop.
3.4.14
ramp
released
The compensation of the voltage loop is installed at the
pin 4 (PFC VCOMP) (see Figure 17). This is the output
of OTA1 and the compensation must be connected at
t
this pin to ground. The compensation is also
responsible for the soft start function which controls an
increasing AC input current during start-up.
13
Combi PFC/ PWM Controller
ICE1CS02
Functional Description
PWM Logic
Current
Limit Latch
Q
S
G1
Limit
L1
R
PWM on
Latch
S
L2
Q
R
Toffmin
400ns
PWM Logic
Voltage Loop
. This loop is closed by the feedback
OUT
. The pin VSENSE is the input of
OUT
Voltage Loop Compensation
25 July 2008
,
OFFMIN
of
MAX
HIGH =
turn GATE on