ICE1CS02G

Manufacturer Part NumberICE1CS02G
DescriptionIC PFC CTRLR AVERAGE CURR DSO16
ManufacturerInfineon Technologies
ICE1CS02G datasheet
 


Specifications of ICE1CS02G

ModeAverage CurrentFrequency - Switching65kHz
Current - Startup1.3mAVoltage - Supply11 V ~ 25 V
Operating Temperature-40°C ~ 150°CMounting TypeSurface Mount
Package / CaseDSO-16Lead Free Status / RoHS StatusLead free / RoHS Compliant
Other namesSP000444092
SP000783614
  
1
2
3
4
5
6
7
8
9
10
11
Page 11
12
Page 12
13
Page 13
14
Page 14
15
Page 15
16
Page 16
17
Page 17
18
Page 18
19
Page 19
20
Page 20
21
22
23
24
25
26
27
Page 14/27

Download datasheet (439Kb)Embed
PrevNext
L1
D1
From
Full-wave
Retifier
R7
Gate Driver
Current Loop
+
PWM Generation
V
IN
Nonlinear
Av(I
)
Gain
IN
t
VCOMP
R6
C4
Figure 16
Voltage Loop
3.4.15
Enhanced Dynamic Response
Due to the low frequency bandwidth of the voltage loop,
the dynamic response is slow and in the range of about
several 10ms. This may cause additional stress to the
bus capacitor and the switching transistor of the PFC in
the event of heavy load changes.
The IC provides therefore a “window detector” for the
feedback voltage V
at pin 2 (PFC VSENSE).
VSENSE
Whenever V
exceeds the reference value (3V)
VSENSE
by +5%, it will act on the nonlinear gain block which in
turn affect the gate drive duty cycle directly. This
change in duty cycle is bypassing the slow changing
VCOMP voltage, thus results in a fast dynamic
response of V
.
OUT
3.4.16
Output Gate Driver
The output gate driver is a fast totem pole gate drive. It
has an in-built cross conduction currents protection and
a Zener diode Z1 (see Figure 18) to protect the external
transistor switch against undesirable over voltages.
The maximum voltage at pin 6 (PFC OUT) is typically
clamped at 15V.
The output is active HIGH and at VCC voltages below
the under voltage lockout threshold VCCUVLO, the
gate drive is internally pull low to maintain the off state.
Version 1.0
Vout
R3
C2
PWM Logic
HIGH to
R4
turn on
GATE
* LV: Level Shift
OTA1
3V
VSENSE
Figure 17
3.5
3.5.1
C5
Figure 18
In the Startup Phase, the IC provides a Soft Start
period to control the maximum primary current by
means of a duty cycle limitation. The Soft start function
14
Combi PFC/ PWM Controller
ICE1CS02
Functional Description
VCC
Gate Driver
LV
Z1
GATE
Gate Driver
PWM Section
Startup Phase
Soft Start
Soft Start counter
SoftS
Soft Start
Soft-Start
Comparator
Gate Driver
C7
&
G8
0.6V
0.4V
x3.2
PWM OP
Soft Start
25 July 2008
External
MOS
CS