ICE1CS02G Infineon Technologies, ICE1CS02G Datasheet - Page 16

• Manufacturer Part Number: ICE1CS02G
• Description: IC PFC CTRLR AVERAGE CURR DSO16
• Manufacturer: Infineon Technologies

Specifications of ICE1CS02G

• Mode: Average Current
• Frequency - Switching: 65kHz
• Current - Startup: 1.3mA
• Voltage - Supply: 11 V ~ 25 V
• Operating Temperature: -40°C ~ 150°C
• Mounting Type: Surface Mount
• Package / Case: DSO-16
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: SP000444092; SP000783614

If Vout is 330V, the duty cycle will be set back to
0.47.The switching frequency is set to f
3.5.4
The output of the oscillator clock will provide
continuous pulse to the PWM-Latch which would turn
on the external MOS switch. After the PWM-Latch is
set, it can be reset by the PWM comparator, the Soft
Start comparator or the Current-Limit comparator.
When it is in reset mode, the output of the driver is
down immediately.
3.5.5
Figure 22
The voltage of the bus voltage is sensed through the
pin 2 (PFC VSENSE). When V
1.95V, the gate signal will stop. When the V
to higher than 2.85V, gate signal will resume again with
soft-start (see Figure 23). The blanking time of 50us is
added in order to avoid the noise interruption.
3.5.6
The output gate driver is a fast totem pole gate drive. It
has an in-built cross conduction currents protection and
a Zener diode Z1 (see Figure 23) to protect the external
transistor switch against undesirable over voltages.
The maximum voltage at pin 8 (PWM OUT) is typically
clamped at 15V.
The output is active HIGH and at VCC voltages below
the under voltage lockout threshold VCCUVLO, the
gate drive is internally pull low to maintain the off state.
Version 1.0
VSENSE
PFC
PWM-Latch FF1
PWM Brown out
Output Gate Driver
PWM brown out circuit
1.95V
2.85V
C12
C11
SENSE
Blanking Time
50us
drops to lower than
switch
R
S
= 130kHz.
SENSE
Q
Q
rises
16
Figure 23
3.5.7
Figure 24
There is a cycle by cycle peak current limiting operation
realized by the Current-Limit comparator C10. The
source current of the MOS switch is sensed via an
external sense resistor R
source current is transformed to a voltage V
which is fed into the PWM CS pin. If this voltage
exceeds the internal threshold voltage V
comparator C10 immediately turns off the gate drive by
resetting
In order to prevent the current limit from distortions
caused by leading edge spikes, a Leading Edge
Blanking is integrated into the current sense path
before connecting to the PWM-OP.
PWM Logic
HIGH to
turn on
* LV: Level Shift
PWM Latch
FF1
Combi PFC/ PWM Controller
Current Limiting
Gate Driver
Current Limiting
the
PW M CS
Gate Driver
LV
PWM-OP
C10
Functional Description
Z1
PWM
Sense
. By means of R
10kΩ
VCC
V
D1
csth
Latch
ICE1CS02
Blanking
25 July 2008
Leading
GATE
220ns
Edge
1pF
External
MOS
Sense
csth
cur_sense
FF1.
the
the