ICE1CS02G

Manufacturer Part NumberICE1CS02G
DescriptionIC PFC CTRLR AVERAGE CURR DSO16
ManufacturerInfineon Technologies
ICE1CS02G datasheet
 


Specifications of ICE1CS02G

ModeAverage CurrentFrequency - Switching65kHz
Current - Startup1.3mAVoltage - Supply11 V ~ 25 V
Operating Temperature-40°C ~ 150°CMounting TypeSurface Mount
Package / CaseDSO-16Lead Free Status / RoHS StatusLead free / RoHS Compliant
Other namesSP000444092
SP000783614
  
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If Vout is 330V, the duty cycle will be set back to
0.47.The switching frequency is set to f
3.5.4
PWM-Latch FF1
The output of the oscillator clock will provide
continuous pulse to the PWM-Latch which would turn
on the external MOS switch. After the PWM-Latch is
set, it can be reset by the PWM comparator, the Soft
Start comparator or the Current-Limit comparator.
When it is in reset mode, the output of the driver is
down immediately.
3.5.5
PWM Brown out
1.95V
C11
PFC
VSENSE
C12
2.85V
Figure 22
PWM brown out circuit
The voltage of the bus voltage is sensed through the
pin 2 (PFC VSENSE). When V
SENSE
1.95V, the gate signal will stop. When the V
to higher than 2.85V, gate signal will resume again with
soft-start (see Figure 23). The blanking time of 50us is
added in order to avoid the noise interruption.
3.5.6
Output Gate Driver
The output gate driver is a fast totem pole gate drive. It
has an in-built cross conduction currents protection and
a Zener diode Z1 (see Figure 23) to protect the external
transistor switch against undesirable over voltages.
The maximum voltage at pin 8 (PWM OUT) is typically
clamped at 15V.
The output is active HIGH and at VCC voltages below
the under voltage lockout threshold VCCUVLO, the
gate drive is internally pull low to maintain the off state.
Version 1.0
= 130kHz.
switch
PWM Logic
HIGH to
turn on
* LV: Level Shift
Figure 23
Blanking Time
3.5.7
50us
R
Q
PWM Latch
FF1
S
Q
drops to lower than
rises
SENSE
Figure 24
There is a cycle by cycle peak current limiting operation
realized by the Current-Limit comparator C10. The
source current of the MOS switch is sensed via an
external sense resistor R
source current is transformed to a voltage V
which is fed into the PWM CS pin. If this voltage
exceeds the internal threshold voltage V
comparator C10 immediately turns off the gate drive by
resetting
In order to prevent the current limit from distortions
caused by leading edge spikes, a Leading Edge
Blanking is integrated into the current sense path
before connecting to the PWM-OP.
16
Combi PFC/ PWM Controller
ICE1CS02
Functional Description
VCC
Gate Driver
LV
Z1
GATE
Gate Driver
Current Limiting
V
csth
Leading
C10
Edge
Blanking
220ns
PWM-OP
1pF
10kΩ
D1
PW M CS
Current Limiting
. By means of R
Sense
the
PWM
Latch
25 July 2008
External
MOS
the
Sense
cur_sense
the
csth
FF1.