E-L6563 STMicroelectronics, E-L6563 Datasheet
E-L6563
Specifications of E-L6563
Related parts for E-L6563
E-L6563 Summary of contents
Page 1
... Remote ON/OFF control ■ Low (≤ 90µA) start-up current ■ 5mA max. quiescent current ■ 1. 25°C) internal reference voltage J ■ -600/+800 mA totem pole gate driver with active pull-down during UVLO ■ SO14 package Figure 1. Block diagram TRACKING BOOST 6 1:1 ...
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... Contents Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.1 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 5 Typical electrical performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 6 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.1 Overvoltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.2 Feedback Failure Protection (FFP 6.3 Voltage Feedforward . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.4 THD optimizer circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6 ...
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... PFC stage (feedback loop failure, boost inductor's core saturation) in the L6563 only and to disable the PFC stage in case of light load for the DC- DC converter make it easier to comply with energy saving norms (Blue Angel, EnergyStar, Energy2000, etc ...
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... Output of the error amplifier. A compensation network is placed between this pin and INV 2 COMP (pin 1) to achieve stability of the voltage control loop and ensure high power factor and low THD. Main input to the multiplier. This pin is connected to the rectified mains voltage via a ...
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... DC-DC converter supplied by the PFC pre-regulator by invoking a latched disable of its PWM controller. If not used, the pin will be left floating. Output pin for fault signaling. During normal operation this pin features high impedance. If the IC is disabled by a voltage below 0.5V on RUN (pin 10) the voltage at the pin is pulled 9 PWM_STOP to ground ...
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... Absolute maximum ratings 2 Absolute maximum ratings Table 3. Absolute maximum ratings Symbol Pin supply voltage (Icc = 20mA --- Analog inputs & outputs to 10 Max. pin voltage (I --- Max. sink current PWM_STOP I 9 Zero current detector max. current ZCD P Power dissipation @T TOT T Junction temperature operating range ...
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... Gain M Error amplifier Voltage feedback input V INV threshold Line regulation I Input bias current INV = 1nF between pin GD and GND Test condition After turn-on (1) (1) Icc = 20 mA Before turn-on, Vcc = 10V After turn-on Latched by PFC_OK > Vthl or Vcs > V CSdis Disabled by PFC_OK < Vth or RUN < ...
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... Output overvoltage Dynamic OVP triggering I OVP current Hys Hysteresis Static OVP threshold Voltage feedforward V Linear operation range VFF Dropout ∆ MULTpk VFF 8/39 = 1nF between pin GD and GND Test condition INV Open loop 2.4 V COMP INV 2.6 V COMP INV I = 0.5 mA ...
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... Clamp voltage clamp PWM_LATCH Low level leakage I leak current V High level H PWM_STOP High level leakage I leak current V Low level L V Clamp voltage clamp = 1nF between pin GD and GND Test condition I = 2.5 mA ZCD 2.5 mA ZCD (4) ( 4.5 V ZCD I = 0.25 mA TBO µA to 0.25 mA TBO (2) ...
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... Current fall time f t Current rise time r V Output clamp voltage Oclamp UVLO saturation (1), (2) Parameters tracking each other (3) The multiplier output is given by: (4) Parameters guaranteed by design, functionality tested in production. 10/39 = 1nF between pin GD and GND Test condition RUN (2) Voltage falling (2) ...
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... Feedback reference vs T (pin 1) (pin 1) 2.6 2.6 Vcc = 12 V Vcc = 12 V 2.55 2.55 2.5 2.5 2.45 2.45 2.4 2.4 -50 - 100 100 Tj (°C) Tj (°C) E/A output clamp levels vs T (pin 2) (pin Upper clamp Upper clamp Vcc = 12 V Vcc = Lower clamp Lower clamp 1 1 -50 -50 ...
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... V V CSoffset (pin 4) CSoffset (pin (mV) (mV) Vcc = 12 V Vcc = 100 100 150 150 Figure 15. Ic latch-off level on current sense vs J Vpin4 Vpin4 2.0 2.0 (V) (V) Vcc = 12 V Vcc = 12 V 1.8 1.8 1.6 1.6 1.4 1.4 1.2 1.2 1.0 1.0 100 100 ...
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... MULT MULT Figure 20. Multiplier gain 0.8 0 0.6 0.6 0.4 0.4 0.2 0 -50 - (°C) Tj (° Figure 17. ZCD clamp levels (pin 2) (pin 2) COMP COMP ZCD (pin 11) ZCD (pin 11) (V) (V) (V) (V) 5.5 5.5 5.0 5.0 4.5 4.5 4.0 4.0 3.5 3.5 3.0 3.0 2.6 2 ...
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... Tj (°C) Tj (°C) 14/39 Figure 23. RUN thresholds Vpin10 Vpin10 (V) (V) Vcc = 12 V Vcc = 100 100 150 150 Figure 25. PWM_LATCH high saturation vs T Vpin8 Vpin8 (V) (V) Vcc = 12 V Vcc = ° °C 400 400 500 500 600 600 Figure 27. PWM_STOP low saturation Vpin9 ...
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... L6563 - L6563A Figure 28. PFC_OK thresholds vs T Vpin7 Vpin7 3.0 3.0 (V) (V) 2.0 2.0 Latch-off Latch-off 1.0 1.0 0.5 0.5 0.3 0 0.2 0.2 OFF OFF 0.1 0.1 -50 - (°C) Tj (°C) Figure 30. Start-up timer vs T Tstart Tstart 150 150 (µs) (µs) Vcc = 12 V Vcc = 12 V ...
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... Overvoltage protection Normally, the voltage control loop keeps the output voltage V close to its nominal value, set by the ratio of the resistors R1 and R2 of the output divider. Neglecting the ripple components, under steady state conditions the current through R1 equals that through R2. Considering that the non-inverting input of the error amplifier is internally biased at 2 ...
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... Example Then 40V/20µA = 2MΩ 2.5·2MΩ·/(400-2.5) = 12.58kΩ. The tolerance on the OVP level due to the L6563/A will be 40·0. that is ± 1.36%. When either OVP is activated the quiescent consumption is reduced to minimize the discharge of the Vcc capacitor. Figure 34. Output voltage setting, OVP and FFP functions: internal block diagram ...
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... When this function is triggered, the gate drive activity is immediately stopped, the device is shut down, its quiescent consumption is reduced below 250 µA and the condition is latched as long as the supply voltage of the IC is above the UVLO threshold. At the same time the pin PWM_LATCH is asserted high. PWM_LATCH is an open source output able to deliver 3 ...
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... Actually, deriving a voltage proportional to the RMS line voltage implies a form of integration, which has its own time constant too small the voltage generated will be affected by a considerable amount of ripple at twice the mains frequency that will cause distortion of the current reference (resulting in high THD and poor PF) ...
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... The amount ripple, related to the amplitude of its 2·f Equation 5 Figure 36 shows a diagram that helps choose the time constant R amount of maximum desired 3 pin, the IC will not work properly if the pin is either left floating or connected directly to ground. Figure 36. R ·C FF current R · ...
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... In this way the THD (Total Harmonic Distortion) of the current is considerably reduced. A major cause of this distortion is the inability of the system to transfer energy effectively when the instantaneous line voltage is very low. This effect is magnified by the high- frequency filter capacitor placed after the bridge rectifier, which retains some residual voltage that causes the diodes of the bridge rectifier to be reverse-biased and the input current flow to temporarily stop ...
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... Furthermore the offset is modulated by the voltage on the V little offset at low line, where energy transfer at zero crossings is typically quite good, and a larger offset at high line where the energy transfer gets worse. The effect of the circuit is shown in PFC controller are compared to those of this chip ...
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... This is commonly referred to as "tracking boost" or "follower boost" approach. With this IC the function can be realized by connecting a resistor (R and ground. The TBO pin presents a DC level equal to the peak of the MULT pin voltage and is then representative of the mains RMS voltage. The resistor defines a current, equal to V(TBO)/R ...
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... Application information to set the output voltage at the desired values use the following design procedure: 1. Determine the input RMS voltage Vin Equation 6 and choose a value Vin output voltage range below Vox (it will equal Vox if one chooses Vin 2. Determine the divider ratio of the MULT pin (pin 3) bias: ...
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... L6563 - L6563A 5. Check that the maximum current sourced by the TBO pin (pin 6) does not exceed the maximum specified (0.25mA): Equation 10 In the following Mathcad® sheet example, the calculation is shown for the circuit illustrated in Figure function. Design data Vin := 88V 1 Vin ...
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... Application information Step 4 ⋅ R2: 2 ⋅ Step 5 3 ------ - TBOmax R Vo(Vi): = Figure 39. Output voltage vs. input voltage characteristic with TBO 400 350 Vo Vin ( ) 300 250 200 26/39 Vin – Vin 2 1 ⋅ -------------------------------------------------------------------------------------------------- ( ) Vin ⋅ 2.5 Vo 2.5 – – – Vin – Vin 2 1 ⋅ ...
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... The voltage drop caused by this abnormal current on the sense resistor reduces the gate-to-source voltage, so that the MOSFET may work in the active region and dissipate a huge amount of power, which leads to a catastrophic failure after few switching cycles. ...
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... PWM controller of the cascaded DC-DC converter to shut down the L6563/A in case of light load, to minimize the no-load input consumption. Should the residual consumption of the chip be an issue also possible to cut down the supply voltage. Interface circuits like those shown in Figure with standby function, can be used ...
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... PFC_STOP The third communication line is the PWM_STOP pin (pin 9), which works in conjunction with the RUN pin (pin 10). The purpose of the PWM_STOP pin is to inhibit the PWM activity of both the PFC stage and the cascaded DC-DC converter. The pin is an open collector, normally open, that goes low if the device is disabled by a voltage lower than 0 ...
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... Application information Figure 44. Interface circuits that let the L6563/A switch on or off a PWM controller If this is not the case not possible to achieve a start-up delay long enough (because this prevents the DC-DC stage from starting up correctly) or, simply, the PWM controller is devoid of soft start, the arrangement of the voltage generated by the PFC stage reaches a preset value ...
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... L6563 - L6563A IC shutdown upon brownout can be easily realized as shown in the left is of general use, the one on the right can be used if the bias levels of the multiplier and the R ·C time constant are compatible with the specified brownout level and with the FF FF specified holdup time respectively ...
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... C7 4.7 nF R10 15.8 kΩ Boost inductor spec: E25x13x7 core, 3C85 ferrite or equivalent 1.6 mm gap for 0.43 mH primary inductance Primary: 80 turns 20 x 0.1 mm Secondary: 9 turns 0.1 mm Figure 48. EVAL6563-80W: PCB and component layout (Top view, real size mm) 32/39 Daux 1N4007 R3B 1N4148 R2 120 kΩ ...
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... L6563 - L6563A Figure 49. EVAL6563-80W: PCB layout, soldering side (Top view) Table 7. EVAL6563-80W: Evaluation results at full load Vin (V ) Pin ( 85.3 115 84.9 135 83.7 180 83.5 230 85.2 265 85.0 Note: Measurements done with the line filter shown in Table 8. EVAL6563-80W: Evaluation results at half load ...
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... Application examples and ideas Figure 50. EVAL6563-80W: Vout vs. Vin relationship (tracking boost) Figure 51. Line filter (not tested for EMI compliance) used for EVAL6563-80W evaluation 34/39 L6563 - L6563A ...
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... Boost Inductor (L1) Spec ETD29x16x10 core, 3C85 ferrite or equivalent 1.5 mm gap for 150 µH primary inductance Primary: 74 turns 20xAWG30 ( Secondary: 8 turns 0.1 mm Figure 53. 350W, wide-range-mains PFC pre-regulator with fixed output voltage and FOT control R1A 620 k R1B C1 B1 620 k 1 µF ...
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... Application examples and ideas Figure 54. Demagnetization sensing without auxiliary winding V inac Figure 55. Enhanced turn-off for big MOSFET driving L6563A 36/39 C ZCD R ZCD ZCD 9 L6563 L6563A Vcc DRIVER L6563 12 GND L6563 - L6563A V out R load Q BC327 Rs ...
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... In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect . The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK trademark. ...
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... Date 13-Nov-2004 24-Sep-2005 17-Nov-2006 12-Mar-2007 38/39 Revision 1 First issue 2 Changed the maturity from “Preliminary data” to “Datasheet” Added new part number L6563A 3 Updated the Section 4 on page 7 document has been reformatted Replaced block diagram, added 4 editor changes. L6563 - L6563A Changes ...
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