E-L6563TR STMicroelectronics, E-L6563TR Datasheet - Page 4

IC CTRLR PFC TRANSITION 14-SOIC

E-L6563TR

Manufacturer Part Number
E-L6563TR
Description
IC CTRLR PFC TRANSITION 14-SOIC
Manufacturer
STMicroelectronics
Datasheet

Specifications of E-L6563TR

Mode
Discontinuous (Transition)
Current - Startup
50µA
Voltage - Supply
10.3 V ~ 22 V
Operating Temperature
-25°C ~ 125°C
Mounting Type
Surface Mount
Package / Case
14-SOIC (3.9mm Width), 14-SOL
Maximum Operating Temperature
+ 150 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 25 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Frequency - Switching
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Description
1.1
1.2
Table 2. Pin description
4/39
Pin N°
1
2
3
4
5
COMP
Name
MULT
VFF
INV
Pin connection
Figure 3.
Pin description
CS
Inverting input of the error amplifier. The information on the output voltage of the PFC pre-
regulator is fed into the pin through a resistor divider.
The pin normally features high impedance but, if the tracking boost function is used, an
internal current generator programmed by TBO (pin 6) is activated. It sinks current from the
pin to change the output voltage so that it tracks the mains voltage.
Output of the error amplifier. A compensation network is placed between this pin and INV
(pin 1) to achieve stability of the voltage control loop and ensure high power factor and low
THD.
Main input to the multiplier. This pin is connected to the rectified mains voltage via a
resistor divider and provides the sinusoidal reference to the current loop. The voltage on
this pin is used also to derive the information on the RMS mains voltage.
Input to the PWM comparator. The current flowing in the MOSFET is sensed through a
resistor, the resulting voltage is applied to this pin and compared with an internal reference
to determine MOSFET’s turn-off.
A second comparison level at 1.7V detects abnormal currents (e.g. due to boost inductor
saturation) and, on this occurrence, shuts down the IC, reduces its consumption almost to
the start-up level and asserts PWM_LATCH (pin 8) high. This function is not present in the
L6563A.
Second input to the multiplier for 1/V
connected from the pin to GND. They complete the internal peak-holding circuit that
derives the information on the RMS mains voltage. The voltage at this pin, a DC level equal
to the peak voltage at pin MULT (pin 3), compensates the control loop gain dependence on
the mains voltage. Never connect the pin directly to GND.
Pin connection (top view)
PFC_OK
COMP
MULT
TBO
VFF
INV
CS
1
2
3
4
5
6
7
2
function. A capacitor and a parallel resistor must be
Description
14
13
12
11
10
9
8
Vcc
GD
GND
ZCD
RUN
PWM_STOP
PWM_LATCH
L6563 - L6563A

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