ADP5020ACPZ-R7 Analog Devices Inc, ADP5020ACPZ-R7 Datasheet - Page 16

IC REG LDO DUAL BUCK 20LFCSP

ADP5020ACPZ-R7

Manufacturer Part Number
ADP5020ACPZ-R7
Description
IC REG LDO DUAL BUCK 20LFCSP
Manufacturer
Analog Devices Inc
Datasheet

Specifications of ADP5020ACPZ-R7

Design Resources
Powering AD9272 with ADP5020 Switching Regulator PMU for Increased Efficiency (CN0135)
Applications
Handheld/Mobile Devices
Current - Supply
10mA
Voltage - Supply
2.4 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
20-LFCSP
Supply Voltage
5.5V
No. Of Step-down Dc - Dc Converters
2
No. Of Ldo Regulators
1
Digital Ic Case Style
LFCSP
No. Of Pins
20
No. Of Regulated Outputs
3
Operating Temperature Range
-40°C To
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
ADP5020ACPZ-R7TR
ADP5020
Table 15. REG_CONTROL_STATUS Register, Address 0x03
Bit
7
6
5
4
3
2
1
0
Table 16. OPERATIONAL_CONTROL Register, Address 0x04
Bit
7
6
5
4
3
2
1
0
1
Table 17. EN_CONTROL Register, Address 0x05
Bit
[7:2]
1
0
The SYNC selection bits (SYNC_AC, SYNC_9P6, and SYNC_19P2) cannot be changed while a switching regulator is running.
Bit Name
BK1_EN
BK2_EN
LDO_EN
EN_ALL
BK1_PGOOD
BK2_PGOOD
LDO_PGOOD
FORCE_XS
Bit Name
Reserved
SYNC_9P6
SYNC_19P2
SYNC_AC
BK1_XSHTDN
BK2_XSHTDN
LDO_XSHTDN
TSD
Bit Name
Reserved
ENO_HIZ_BAR
ENO_DRV
1
1
1
Access
R/W
R/W
R/W
R/W
R
R
R
R/W
Access
N/A
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Access
N/A
R/W
R/W
Default
0
0
0
0
0
0
0
0
Default
N/A
0
0
0
Fuse
Fuse
Fuse
0
Default
N/A
0
0
Description
1 = turns on the Buck 1 regulator. If the EN pin is high, the sequencer is ignored.
1 = turns on the Buck 2 regulator. If the EN pin is high, the sequencer is ignored.
1 = turns on the LDO regulator. If the EN pin is high, the sequencer is ignored.
1 = turns on all regulators, following sequencer programming. BK1_EN, BK2_EN, and
LDO_EN must all be set to 0 for this bit to function.
Power good status for Buck 1.
1 = power good (POK).
0 = fail.
Power good status for Buck 2.
1 = power good (POK).
0 = fail.
Power good status for LDO.
1 = power good (POK).
0 = fail.
1 = the XSHTDN pin is controlled by the power good signals.
0 = the XSHTDN pin is held low unless the EN pin is high, regardless of regulator status.
If EN is high, this bit is ignored in controlling the XSHTDN pin (acts as if FORCE_XS = 1).
Description
Reserved.
1 = a 9.6 MHz clock is on the SYNC pin. The SYNC frequency is divided by 3 and used as
clock frequency for switching regulators.
1 = a 19.2 MHz clock is on the SYNC pin. The SYNC frequency is divided by 6 and used as
clock frequency for switching regulators.
1 for both SYNC_9P6 and SYNC_19P2 = invalid setting.
0 for both SYNC_9P6 and SYNC_19P2 = clock synchronization is disabled, and the device
operates with the 3 MHz internal clock.
1 = the ac path is used for the SYNC input.
0 = the dc path is used (default).
0 = power good for Buck 1 must be high for XSHTDN to go high (default).
1 = Buck 1 power good is ignored.
0 = power good for Buck 2 must be high for XSHTDN to go high (default).
1 = Buck 2 power good is ignored.
0 = LDO power good must be high for XSHTDN to go high (default).
1 = LDO power good is ignored.
Shows a latched status of a thermal shutdown (TSD) event.
1 = TSD is active.
Must be cleared to 0 by user program to enable the regulators. If this bit remains set to 1,
regulator activation is inhibited, as in a thermal shutdown event.
Description
Reserved.
0 = the EN/GPIO pin is in high impedance, and the EN function is selected.
1 = GPIO output is selected, and the EN function is ignored.
Active only when ENO_HIZ_BAR = 1 (GPIO).
0 = GPIO output is set to low.
1 = GPIO output is set to high.
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