IR3081AMTRPBF International Rectifier, IR3081AMTRPBF Datasheet
IR3081AMTRPBF
Specifications of IR3081AMTRPBF
IR3081AMTRPBFTR
IR3081AMTRPBFTR
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IR3081AMTRPBF Summary of contents
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DESCRIPTION The IR3081A Control IC combined with an IR XPhase to implement a complete VR 10 power solution. The “Control” IC provides overall system control and interfaces with any number of “Phase ICs” which each drive and monitor a single ...
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... POWERGOOD ENABLE 1 OSCDS VID5 2 VID5 VID0 3 IR3081A VID0 VID1 4 CONTROL VID1 VID2 5 IC VID2 VID3 6 VID3 VID4 7 VID4 ORDERING INFORMATION Device IR3081AMTRPbF IR3081AMPbF Page CVCC 0.1uF 21 0.1uF VBIAS 20 BBFB 19 EAOUT RCP VDRP CDRP RDRP1 16 IIN RDRP 15 OCSET ROCSET CFB ROSC RVDAC ...
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ABSOLUTE MAXIMUM RATINGS Operating Junction Temperature……………..150 Storage Temperature Range………………….-65 ESD Rating………………………………………HBM Class 1C JEDEC standard PIN # PIN NAME 1 OSCDS 2-7 VID0 TRM1-4 11,12 10 VOSNS- 13 ROSC 14 VDAC 15 OCSET 16 IIN 17 VDRP 18 ...
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ELECTRICAL SPECIFICATIONS Unless otherwise specified, these specifications apply over: 9.5V ≤ V PARAMETER VDAC Reference System Set-Point Accuracy Source Current Sink Current VID Input Threshold VID Input Bias Current Regulation Detect Comparator Input Offset Regulation Detect to EAOUT Delay BBFB ...
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PARAMETER Oscillator Switching Frequency Peak Voltage (5V typical, measured VBIAS) Valley Voltage (1V typical, measured VBIAS) VBIAS Regulator Output Voltage Current Limit Soft Start and Delay SS/DEL to FB Input Offset Voltage Charge Current ...
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PIN DESCRIPTION PIN# PIN SYMBOL PIN DESCRIPTION 1 OSCDS Apply a voltage greater than VBIAS to disable the oscillator. Used during factory testing & trimming. Ground or leave open for normal operation. 2-7 VID0-5 Inputs to VID ...
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SYSTEM THEORY OF OPERATION TM XPhase Architecture TM The XPhase architecture is designed for multiphase interleaved buck converters which are used in applications requiring small size, design flexibility, low voltage, high current and fast transient response. The architecture can control ...
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PWM Control Method The PWM block diagram of the XPhase trailing edge modulation is used. A high-gain wide-bandwidth voltage type error amplifier in the Control IC is used for the voltage control loop. An external RC circuit connected to the ...
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VPEAK (5.0V) VPHASE4&5 (4.5V) VPHASE3&6 (3.5V) VPHASE2&7 (2.5V) VPHASE1&8 (1.5V) VVALLEY (1.00V) PWM Operation The PWM comparator is located in the Phase IC. Upon receiving a clock pulse, the PWM latch is set; the PWMRMP voltage begins to increase; the ...
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PHASE IC CLOCK PULSE EAIN PWMRMP VDAC GATEH GATEL STEADY-STATE OPERATION TM Body Braking In a conventional synchronous buck converter, the minimum time required to reduce the current in the inductor in response to a load step decrease is; The ...
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Figure 5. Inductor Current Sensing and Current Sense Amplifier The advantage of sensing the inductor current versus high side or low side sensing is that actual output current being delivered to the load is obtained rather than peak or sampled ...
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IR3081A THEORY OF OPERATION Block Diagram The Block diagram of the IR3081A is shown in Fig. 6, and specific features are discussed in the following sections. VCC UVLO COMPARATOR VCC - START STOP + + 9.7V 0.2V 8.9V - ENABLE ...
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The IR3081A can accept changes in the VID code while operating and vary the DAC voltage accordingly. The sink/source capability of the VDAC buffer amplifier is programmed by the same external resistor that sets the oscillator frequency. The slew rate ...
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Processor Pins (0 = low high) VID4 VID3 VID2 VID1 ...
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Control IC VDAC Inductor DCR Temperature Correction If the thermal compensation of the inductor DCR provided by the temperature dependent gain of the current sense amplifier is not adequate, a negative temperature coefficient (NTC) thermistor can be used for additional ...
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Soft Start, Over-Current Fault Delay, and Hiccup Mode The IR3081A has a programmable soft-start function to limit the surge current during the converter start-up. A capacitor connected between the SS/DEL and LGND pins controls soft start as well as over-current ...
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VCC (12V) ENABLE 3.735V 3.685V SS/DEL 1.3V VOUT PWRGD IOUT START-UP NORMAL OPERATION (ENABLE GATES (VOUT CHANGES DUE TO LOAD FAULT MODE) AND VID CHANGES) Power Good Output The PWRGD pin is an open-collector output and should be pulled up ...
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APPLICATION INFORMATION 12V QGATE RVCC VGATE 10 ohm DGATE RGATE CVCC 0.1uF 0.1uF ENABLE RBBFB 1 21 OSCDS VBIAS VID5 2 20 VID5 BBFB VID0 IR3081A 3 19 VID0 EAOUT CONTROL VID1 4 18 VID1 FB VID2 ...
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DESIGN PROCEDURES - IR3081A AND IR3086A CHIPSET IR3081A EXTERNAL COMPONENTS Oscillator Resistor Rosc The oscillator of IR3081A generates a triangle waveform to synchronize the phase ICs, and the switching frequency of the each phase converter equals the oscillator frequency, which ...
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Over Current Setting Resistor R The inductor DC resistance is utilized to sense the inductor current. The copper wire of inductor has a constant temperature coefficient of 3850 ppm/°C, and therefore the maximum inductor DCR can be calculated from Equation ...
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IR3086A EXTERNAL COMPONENTS PWM Ramp Resistor R and Capacitor C PWMRMP PWM ramp is generated by connecting the resistor R as the capacitor C between PWMRMP and LGND. Choose the desired PWM ramp magnitude V PWMRMP the capacitor C in ...
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Phase Delay Timing Resistors R The phase delay of the interleaved multiphase converter is programmed by the resistor divider connected at RMPIN+ or RMPIN- depending on which slope of the oscillator ramp is used for the phase delay programming of ...
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VOLTAGE LOOP COMPENSATION The adaptive voltage positioning (AVP) is usually adopted in the computer applications to improve the transient response and reduce the power loss at heavy load. Like current mode control, the adaptive voltage positioning loop introduces extra zero ...
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A tan Choose the desired crossover frequency fc around fc1 estimated by Equation (27) or choose fc between 1/10 and 1/5 of the switching frequency per phase, and select the components to ensure the ...
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CURRENT SHARE LOOP COMPENSATION The crossover frequency of the current share loop should be at least one decade lower than that of the voltage loop in order to eliminate the interaction between the two loops. A capacitor from SCOMP to ...
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DESIGN EXAMPLE 1 - VRM 10 2U CONVERTER SPECIFICATIONS Input Voltage DAC Voltage: V =1.35 V DAC No Load Output Voltage Offset: V Output Current: I =105 ADC O Maximum Output Current: I =120 ADC OMAX ...
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VDAC Slew Rate Programming Capacitor C From Figure 15, the sink current of VDAC pin corresponding to 400kHz (R VDAC down-slope slew-rate programming capacitor from the required down-slope slew rate. − SINK = = C ...
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Body Braking Related Resistors R N/A. The body braking during Dynamic VID is disabled. IR3086A EXTERNAL COMPONENTS PWM Ramp Resistor R and Capacitor C PWMRMP Set PWM ramp magnitude V PWMRMP resistor R , PWMRMP = R PWMRMP ∗ ∗ ...
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Bootstrap Capacitor C BST Choose C =0.1uF BST Decoupling Capacitors for Phase IC and Power Stage Choose C =0.1uF, C =0.1uF VCC VCCL VOLTAGE LOOP COMPENSATION Type II compensation is used for the converter with AL-Polymer output capacitors. Choose the ...
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DESIGN EXAMPLE 2 - EVRD 10 HIGH FREQUENCY ALL-CERAMIC CONVERTER SPECIFICATIONS Input Voltage DAC Voltage: V =1.3 V DAC No Load Output Voltage Offset: V Output Current: I =105 ADC O Maximum Output Current: I =120 ...
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I 170 * 10 SINK = = C VDAC − − DOWN Calculate the programming resistor. − ...
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IR3086A EXTERNAL COMPONENTS PWM Ramp Resistor R and Capacitor C PWMRMP Set PWM ramp magnitude V PWMRMP resistor R , PWMRMP = R PWMRMP [ln PWMRMP = − ∗ ∗ ...
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R =10kΩ, R =768Ω, R PHASE41 PHASE42 Bootstrap Capacitor C BST Choose C =0.1uF BST Decoupling Capacitors for Phase IC and Power Stage Choose C =0.1uF, C =0.1uF VCC VCCL VOLTAGE LOOP COMPENSATION Type III compensation is used for the ...
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LAYOUT GUIDELINES The following layout guidelines are recommended to reduce the parasitic inductance and resistance of the PCB layout, therefore minimizing the noise coupled to the IC. • Dedicate at least one middle layer for a ground plane LGND. • ...
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PCB Metal and Component Placement • Lead land width should be equal to nominal part lead width. The minimum lead to lead spacing should be ≥ 0.2mm to minimize shorting. • Lead land length should be equal to maximum part ...
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Solder Resist • The solder resist should be pulled away from the metal lead lands by a minimum of 0.06mm. The solder resist mis-alignment is a maximum of 0.05mm and it is recommended that the lead lands are all Non ...
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Stencil Design • The stencil apertures for the lead lands should be approximately 80% of the area of the lead lands. Reducing the amount of solder deposited will minimize the occurrence of lead shorts. Since for 0.5mm pitch devices the ...
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PERFORMANCE CHARACTERISTICS Page Figure 13 - Oscillator Frequency versus ROSC 1000 950 900 850 800 750 700 650 600 550 500 450 400 350 300 250 200 150 ...
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PACKAGE INFORMATION 28L MLPQ ( Body) – θ IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 www.irf.com Page C/W, θ JA Data and specifications subject ...