ISL6548ACRZA-T Intersil, ISL6548ACRZA-T Datasheet - Page 16

• Manufacturer Part Number: ISL6548ACRZA-T
• Description: IC REG/CTLR ACPI DUAL DDR 28QFN
• Manufacturer: Intersil

Specifications of ISL6548ACRZA-T

• Applications: Memory, DDR/DDR2 Regulator
• Current - Supply: 7mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 28-QFN
• Rohs Compliant: YES
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Supply: -
• Other names: ISL6548ACRZA-T

Quad Flat No-Lead Plastic Package (QFN)
Micro Lead Frame Plastic Package (MLFP)
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
For information regarding Intersil Corporation and its products, see www.intersil.com
16
ISL6548A
L28.6x6
28 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
(COMPLIANT TO JEDEC MO-220VJJC ISSUE C)
NOTES:
10. Depending on the method of lead termination at the edge of the
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
3. Nd and Ne refer to the number of terminals on each D and E.
4. All dimensions are in millimeters. Angles are in degrees.
5. Dimension b applies to the metallized terminal and is measured
6. The configuration of the pin #1 identifier is optional, but must be
7. Dimensions D2 and E2 are for the exposed pads which provide
8. Nominal dimensions are provided to assist with PCB Land Pattern
9. Features and dimensions A2, A3, D1, E1, P & θ are present when
SYMBOL
between 0.15mm and 0.30mm from the terminal tip.
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
improved electrical and thermal performance.
Design efforts, see Intersil Technical Brief TB389.
Anvil singulation method is used and not present for saw
singulation.
package, a maximum 0.15mm pull back (L1) maybe present. L
minus L1 to be equal to or greater than 0.3mm.
A1
A2
A3
D1
D2
E1
E2
Nd
Ne
L1
A
D
E
N
P
b
e
k
L
θ
0.80
0.23
3.95
3.95
0.25
0.35
MIN
-
-
-
-
-
MILLIMETERS
NOMINAL
6.00 BSC
5.75 BSC
6.00 BSC
5.75 BSC
0.20 REF
0.65 BSC
0.90
0.28
4.10
4.10
0.60
28
7
7
-
-
-
-
-
-
MAX
1.00
0.05
1.00
0.35
4.25
4.25
0.75
0.15
0.60
12
-
Rev. 1 10/02
January 3, 2006
NOTES
FN9189.2
5, 8
7, 8
7, 8
10
9
9
9
9
8
2
3
3
9
9
-
-
-
-
-
-